Patents by Inventor Hung Yu

Hung Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12010413
    Abstract: There is provided an optical engine for a navigation device including a first light source, a second light source, a lens, a carrier member and an image sensor. The carrier member has a light holder, a lens holder, an accommodation space and a tilted wall. The first light source is arranged on the light holder of the carrier member, and reflected light associated with the first light source penetrates through the lens to propagate to the image sensor inside the accommodation space. Reflected light associated with the second light source penetrates through the tilted wall of the carrier member to propagate to the image sensor.
    Type: Grant
    Filed: June 15, 2022
    Date of Patent: June 11, 2024
    Assignee: PIXART IMAGING INC.
    Inventors: Yen-Hung Wang, Wen-Yen Su, Hui-Hsuan Chen, Hung-Yu Lai
  • Publication number: 20240188303
    Abstract: An apparatus for novel high-speed low power non-volatile memory for the next generation electronic memory and computing technology is provided. The apparatus may include a ferroelectric tunnel junction (FTJ) that can switch between two or more conductance states in a reversible and non-volatile manner. A ferroelectric tunnel junction (FTJ) having two electrodes separated by a thin ferroelectric (FE) insulating layer has potential to replace existing volatile and non-volatile memory. Through the application of electrical pulses, the electrical resistance of an FTJ can be reversibly changed in a non-volatile manner by switching the ferroelectric polarization in the ferroelectric insulator layer.
    Type: Application
    Filed: June 22, 2022
    Publication date: June 6, 2024
    Applicant: UNIVERSITY OF SOUTHERN CALIFORNIA
    Inventors: Han Wang, Jiang-Bin Wu, Hung-Yu Chen
  • Patent number: 12001026
    Abstract: A head-mounted display includes a display device, a connecting structure and a head abutting portion. The connecting structure is in a shape of strip. The connecting structure has two opposite ends. The ends are respectively connected with the display device. The connecting structure and the display device define an accommodation space. The accommodation space is configured to accommodate a head of a user. The head abutting portion is pivotally connected with the connecting structure. The head abutting portion is at least partially located between the connecting structure and the display device. The head abutting portion is configured to abut against the head of the user.
    Type: Grant
    Filed: September 13, 2021
    Date of Patent: June 4, 2024
    Assignee: Quanta Computer Inc.
    Inventors: Hung-Yu Lin, Chun-Feng Yeh, Jia-Cheng Chang, Bing-Kai Huang, Chun-Nan Huang, Chun-Lung Chen
  • Publication number: 20240178003
    Abstract: A method for processing a substrate that includes: depositing a filling material over the substrate including a first recess and a second recess, the filling material filling the first recess and the second recess; patterning the filling material such that the first recess is reopened while the second recess remains filled with the filling material; filling the first recess with a conductive material to a first height; etching the filling material selectively to the conductive material to reopen the second recess; filling a remainder of the first recess and the second recess with the conductive material; and performing an etch back process to etch the conductive material such that the first recess and the second recess are filled with the conductive material to a second height.
    Type: Application
    Filed: November 28, 2022
    Publication date: May 30, 2024
    Inventors: Hirokazu Aizawa, Kai-Hung Yu, Nicholas Joy, Yusuke Yoshida, Kandabara Tapily
  • Publication number: 20240179891
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, an isolation feature, a word line and a doped region. The substrate has an active region. The isolation feature is disposed in the substrate to define the active region. The word line is buried in the substrate and extends across the active region and the isolation feature. The word line includes a first conductive structure and a second conductive structure disposed on the first conductive structure. The doped region is disposed in the active region and adjacent to the word line, wherein a top surface of the first conductive structure is below a bottom surface of the doped region.
    Type: Application
    Filed: November 30, 2022
    Publication date: May 30, 2024
    Inventor: Hung-Yu WEI
  • Patent number: 11997935
    Abstract: A resistive random-access memory (RRAM) device, including a bottom electrode, a high work function layer, a resistive material layer and a top electrode sequentially stacked on a substrate, wherein the resistive material layer includes a bottom part and a top part, first spacers covering sidewalls of the top part and the top electrode, and second spacers covering sidewalls of the bottom part, thereby constituting a RRAM cell.
    Type: Grant
    Filed: September 27, 2022
    Date of Patent: May 28, 2024
    Assignee: UNITED MICROELECTRONICS CORP.
    Inventors: Shu-Hung Yu, Chun-Hung Cheng, Chuan-Fu Wang
  • Patent number: 11991482
    Abstract: An illumination system, a projection device, and a projection control method are provided. The illumination system includes a first light-emitting unit, a second light-emitting unit, a third light-emitting unit, a first dichroic element, a second dichroic element, and a control unit. The first light-emitting unit includes a first light-emitting element and a second light-emitting element. The control unit is electrically connected to the first light-emitting unit and configured to switch the illumination system between a high-performance mode and a high-chroma mode, wherein when the illumination system is in the high-performance mode, the control unit controls a current ratio of the second light-emitting element to be greater than a current ratio of the first light-emitting element, and when the illumination system is in the high-chroma mode, the control unit controls the current ratio of the second light-emitting element to be less than the current ratio of the first light-emitting element.
    Type: Grant
    Filed: October 28, 2022
    Date of Patent: May 21, 2024
    Assignee: Coretronic Corporation
    Inventors: Chi-Fu Liu, Tsung-Hsin Liao, Chun-Li Chen, Hung-Yu Lin
  • Patent number: 11991932
    Abstract: A magnetic tunnel junction device includes a pillar structure including, from bottom to top, a bottom electrode and a magnetic tunnel junction structure, a top electrode overlying the magnetic tunnel junction structure, and a dielectric metal oxide layer extending from a sidewall of the pillar structure to a sidewall of the top electrode. The magnetic tunnel junction structure contains a reference magnetization layer including a first ferromagnetic material, a tunnel barrier layer, and a free magnetization layer including a second ferromagnetic material. The top electrode includes a metallic material containing a nonmagnetic metal element. The dielectric metal oxide layer may be formed by performing an oxidation process that oxidizes a residual metal film after a focused ion beam etch process, and eliminates conductive paths from surfaces of the pillar structure.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: May 21, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hung-Yu Chang, Min-Yung Ko
  • Publication number: 20240162809
    Abstract: A power supply circuit is provided. The power factor correction (PFC) circuit is used to perform a power factor correction according to a first voltage to generate an intermediate voltage. The first storage capacitor is used to store a first electrical energy related to the intermediate voltage. The boost conversion circuit is connected to the PFC circuit and used to generate an output voltage according to the intermediate voltage. The boost conversion circuit includes a first post-stage inductor, a first post-stage diode and a first post-stage transistor. The second storage capacitor is used to store a second electrical energy related to the output voltage. The capacitance value of the second storage capacitor is less than the capacitance value of the first storage capacitor; the first electrical energy is completely or partially transferred as the second electrical energy.
    Type: Application
    Filed: March 6, 2023
    Publication date: May 16, 2024
    Inventors: Yu-Cheng LIN, Te-Hung YU, Chia-Hui LIANG, Min-Hao HSU
  • Publication number: 20240159642
    Abstract: A smoke detector with an anti-insect function includes a substrate, an optical detection module, a top cover, a base and a perforated plate. The substrate has a ring shape region surrounding a central detection region, and a first block structure of the central detection region is protruded from the substrate and higher than an upper surface of the ring shape region. The optical detection module is disposed inside the central detection region. The top cover has a lateral wall. The base is disposed on the substrate and connected to the top cover to cover the optical detection module. The base has a second block structure partly overlapped with the lateral wall to form a guiding channel. The perforated plate is disposed between the lateral wall and the second block structure to prevent an insect from moving into the top cover through the guiding channel.
    Type: Application
    Filed: January 25, 2024
    Publication date: May 16, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Yen-Chang Chu, Cheng-Nan Tsai, Chih-Ming Sun, Zhi-Hao Wu, Hung-Yu Lai
  • Publication number: 20240151707
    Abstract: A fabric feature predicting method includes following operations: measuring multiple first fabrics to generate multiple first fabric actual feature value groups; storing the first fabric actual feature value groups and multiple first fabric information groups of the first fabrics; selecting multiple third fabrics from the first fabrics according to a second fabric information group of a second fabric; generating at least one equation according to multiple third fabric actual feature value groups of the third fabrics and multiple third fabric information groups of the third fabrics; generating a second fabric predicted feature value group of the second fabric according to the at least one equation and the second fabric information group. The first fabric actual feature value groups include the third fabric actual feature value groups. The first fabric information groups include the third fabric information groups.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 9, 2024
    Inventors: Hung-Yu LIN, Pei-Te SHEN, Chin-Lun CHU, Tzu-Yu CHIU, Yu-Sian CIOU
  • Publication number: 20240152246
    Abstract: A joystick includes a stick head, an actuating component, a substrate, a bearing base, a resilient recovering component, a first rotation component and a second rotation component. The actuating component has a first end and a second end opposite to each other. The first end is connected to the stick head, and an identification feature is disposed on the second end. The substrate has a detector used to detect the identification feature and determine motion of the stick head. The bearing base is disposed on the substrate. The resilient recovering component is disposed between the substrate and the bearing base. The first rotation component is movably disposed on the bearing base and rotatable in a first direction. The second rotation component is movably connected to the first rotation component and rotatable in a second direction different from the first direction, and connected to the actuating component in a rotatable manner.
    Type: Application
    Filed: January 16, 2024
    Publication date: May 9, 2024
    Applicant: PixArt Imaging Inc.
    Inventors: Hung-Yu Lai, Yong-Nong Huang, Hui-Hsuan Chen, Jia-Hong Huang
  • Publication number: 20240153781
    Abstract: Embodiments of methods are provided for thermal dry etching of a ruthenium (Ru) metal layer. In the disclosed embodiments, a substrate containing a Ru metal layer formed thereon is exposed to a gas pulse sequence, while the substrate is held at a relatively high substrate temperature (e.g., a temperature greater than or equal to about 160° C.), to provide thermal etching of the Ru metal layer. As described further herein, the gas pulse sequence may generally include a plurality of gas pulses, which are supplied to the substrate sequentially with substantially no overlap between gas pulses. The gas pulses supplied to the substrate form: (i) volatile reaction products that are vaporized from the Ru surface, and (ii) non-volatile oxide surface layers that are removed from the Ru surface by the next gas pulse, resulting in atomic layer etching (ALE) of the Ru metal layer.
    Type: Application
    Filed: October 31, 2023
    Publication date: May 9, 2024
    Inventors: Hisashi Higuchi, Kai-Hung Yu, Cory Wajda, Gyanaranjan Pattanaik, Kandabara Tapily, Gerrit Leusink, Robert Clark
  • Publication number: 20240154517
    Abstract: A soft-switching power converter includes a main switch, an energy-releasing switch, and an inductive coupled unit. The main switch is a controllable switch. The energy-releasing switch is coupled to the main switch. The inductive coupled unit is coupled to the main switch and the energy-releasing switch. The inductive coupled unit includes a first inductance, a second inductance coupled to the first inductance, and an auxiliary switch unit. The auxiliary switch unit is coupled to the second inductance to form a closed loop. The main switch and the energy-releasing switch are alternately turned on and turned off. The auxiliary switch unit is controlled to start turning on before the main switch is turned on so as to provide at least one current path.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Hung-Chieh LIN, Yi-Ping HSIEH, Jin-Zhong HUANG, Hung-Yu HUANG, Chih-Hsien LI, Ciao-Yin PAN
  • Publication number: 20240153992
    Abstract: A device includes a first channel structure, a second channel structure, and a gate structure. The first channel structure connects a first source region and a first drain region, and includes alternating stacking first semiconductor layers and second semiconductor layers. The second semiconductor layers have a width smaller than a width of the first semiconductor layers. The second channel structure connects a second source region and a second drain region. The second channel structure includes alternating stacking third semiconductor layers and fourth semiconductor layers. The fourth semiconductor layers have a width smaller than a width of the third semiconductor layers. The gate structure wraps around the first and second channel structures.
    Type: Application
    Filed: January 11, 2024
    Publication date: May 9, 2024
    Applicants: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., NATIONAL TAIWAN UNIVERSITY
    Inventors: Hung-Yu YE, Yu-Shiang HUANG, Chien-Te TU, Chee-Wee LIU
  • Publication number: 20240143791
    Abstract: The invention introduces an apparatus for detecting errors during data encryption. The apparatus includes a search circuitry and a substitution check circuitry. The key generation circuitry is arranged operably to convert a first value of one byte corresponding to a plaintext, an intermediate encryption result, or a round key into a second value of a K-bit according to an 8-to-K lookup table, where K is an integer ranging from 10 to 15 and the second value comprises (K minus 8) bits of a Hamming parity. The substitution check circuitry is arranged operably to employ check formulae corresponding to the 8-to-K lookup table to determine whether an error is occurred during a conversion of the first value of the one byte into the second value of the K-bit, and output an error signal when finding the error, where a total amount of the formulae is K minus 8.
    Type: Application
    Filed: May 30, 2023
    Publication date: May 2, 2024
    Applicant: Silicon Motion, Inc.
    Inventors: Wun-Jhe WU, Po-Hung CHEN, Chiao-Wen CHENG, Jiun-Hung YU, Chih-Wei LIU
  • Patent number: 11973052
    Abstract: An electronic device includes a bond wire with a first end bonded by a ball bond to a planar side of a first conductive plate, and a second end bonded by a stitch bond to a conductive stud bump at an angle greater than or equal to 60 degrees. A wirebonding method includes bonding the first end of the conductive bond wire to the first conductive plate includes forming a ball bond to join the first end of the conductive bond wire to a planar side of the first conductive plate by a ball bond, and bonding the second end of the conductive bond wire to the conductive stud bump includes forming a stitch bond to join the second end of the conductive bond wire to the conductive stud bump.
    Type: Grant
    Filed: April 28, 2021
    Date of Patent: April 30, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Chien-Chang Li, Hung-Yu Chou, Sheng-Wen Huang, Zi-Xian Zhan, Byron Lovell Williams
  • Patent number: 11972353
    Abstract: Some embodiments herein can include methods and systems for predicting next poses of a character within a virtual gaming environment. The pose prediction system can identify a current pose of a character, generate a gaussian distribution representing a sample of likely poses based on the current pose, and apply the gaussian distribution to the decoder. The decoder can be trained to generate a predicted pose based on a gaussian distribution of likely poses. The system can then render the predicted next pose of the character within the three-dimensional virtual gaming environment. Advantageously, the pose prediction system can apply a decoder that does not include or use input motion capture data that was used to train the decoder.
    Type: Grant
    Filed: January 21, 2021
    Date of Patent: April 30, 2024
    Assignee: Electronic Arts Inc.
    Inventors: Fabio Zinno, George Cheng, Hung Yu Ling, Michiel van de Panne
  • Publication number: 20240138030
    Abstract: An electrothermal module includes a first conductive layer, a second conductive layer, and a heat generating layer. The first conductive layer and the second conductive layer respectively include silver metal. The heat generating layer has a first portion, the first portion is disposed between the first conductive layer and the second conductive layer to form an electrothermal conversion portion of the electrothermal module, and the heat generating layer includes a conductive carbon material.
    Type: Application
    Filed: September 26, 2023
    Publication date: April 25, 2024
    Inventors: Hou-Sheng HUANG, Chien-Lung SHEN, Shu-Chu TSAI, Hung-Yu LIN
  • Patent number: D1026910
    Type: Grant
    Filed: November 7, 2023
    Date of Patent: May 14, 2024
    Assignee: HTC CORPORATION
    Inventors: Shu-Kuen Chang, Natalia Amijo, Ian James McGillivray, Chin-Wei Chou, Yi-Shen Wang, Chih-Sung Fang, Hung-Yu Chen