Abstract: A semiconductor device includes a substrate, a plurality of active structures, a trench, a lower epitaxy, an upper epitaxy and a bottom barrier portion. The active structures are formed on the substrate and arranged in a first direction. The trench passes through adjacent two of the active structures in a second direction and has a bottom recess. The lower epitaxy is formed on a lower portion of the trench. The upper epitaxy is formed on an upper portion of the trench and separated from the lower epitaxy. The bottom barrier portion is formed on the bottom recess and separates the substrate and the lower epitaxy.

Abstract: A switch mode power supply circuit with high voltage output, an electrostatic spray apparatus and agricultural plant protection apparatus using the same are provided. The switch mode power supply circuit is electrically connected in series with at least a pre-stage power converter and a post-stage power converter. In order to simplify the control, the switch of the pre-stage power converter is omitted, only one switch of the post-stage power converter is adopted to perform synchronous control. Since the multiple sets of power conversion circuits in the previous stage are connected in series, the turn ratio of the transformer in the power converter in the subsequent stage can be reduced. Therefore, the transformer can be miniaturized and the power supply circuit would be more suitable for agricultural plant protection machine and electrostatic spray apparatus.

Abstract: A core test method, for testing a processing circuit with multi cores, comprising: (a) testing defects of the cores to determine at least one failed core; (b) recording the failed core; (c) performing a performance test to all of the cores to generate performance data; and (d) filtering the performance data based on the failed core recorded in the step (b).

Abstract: A forming method of a ReRAM array includes steps as follows: Firstly, a first pulse is applied to a first ReRAM unit in the ReRAM array. Afterwards, a second pulse is applied to the first ReRAM unit, wherein the electrical property of the first pulse is opposite to that of the second pulse. Then, a verification pulse is applied to the first ReRAM unit to verify whether the first resistance value of the first ReRAM unit passes a preset threshold. When the first resistance value passes the preset threshold value, a third pulse is applied to the first ReRAM unit, wherein the first pulse and the third pulse have the same electrical property, and the first pulse has a voltage value substantially the same to that of the third pulse.

Abstract: The present invention relates to a driving method for flicker suppression of a display panel and a driving circuit thereof. The driving circuit includes a source driving circuit and a common voltage generating circuit. The driving method includes driving the source driving circuit to generate at least one first source signal and at least one second source signal, the first source signal corresponds to at least one first pixel on a first scanning line; the second source signal corresponds to at least one second pixel on a second scanning line. The common voltage generating circuit generates at least one common voltage. While driving the first pixel and the second pixel to display the same gray scale image, the first source signal is not equal to the second source signal, or a first common voltage and a second common voltage generated by the common voltage generating circuit are different.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a first source/drain region and a second source/drain region disposed within the substrate, and a gate structure disposed on the substrate and between the first source/drain region and the second source/drain region. The semiconductor device further includes an interlayer dielectric layer disposed over the first source/drain region, the second source/drain region, and the gate structure. The interlayer dielectric layer includes a second trench extending into the second source/drain region. The semiconductor device further includes a dielectric layer disposed in the second trench, and a second source/drain contact disposed over the second source/drain region and filling the remaining portion of the second trench.

Abstract: A user equipment includes a processor and a transmitter. The processor performs a neural network computation to generate neural network computation results. The neural network computation results are intermediate data of the neural network computation. The intermediate data are the neural network computation results of computation nodes in partial layers of the neural network computation. The transmitter transmits a data packet to a base station to perform computation of computation nodes in remaining layers of the neural network computation. The data packet includes the neural network computation results, a packet header, and a descriptor. The descriptor includes parameters and settings of the neural network computation results. The parameters and settings include at least two of a neural network type, number of layers in the neural network, a size of the neural network computation results, level of the neural network computation results, a sequence number, and a time stamp.

Abstract: In an embodiment, a method includes: forming a sacrificial spacer in a contact opening, the contact opening exposing a source/drain region; depositing a spacer layer on a sidewall of the sacrificial spacer and on a top surface of the source/drain region; forming a protective dielectric on the spacer layer and in the contact opening; removing the sacrificial spacer to form a recess adjacent the spacer layer; and forming a dielectric cap in an upper portion of the recess by redepositing a material of the protective dielectric and a material of the spacer layer in the upper portion of the recess, the dielectric cap sealing a lower portion of the recess to form a void.

Abstract: A multi-gate semiconductor structure and its manufacturing method are provided. The semiconductor structure includes a substrate having an active area and an isolation structure adjacent to the active area. The semiconductor structure includes a gate structure formed on the substrate and a gate dielectric layer between the gate structure and the substrate. The gate structure includes a first part above the top surface of the substrate and a second part connected to the first part. The second part of the gate structure is formed in the isolation structure, wherein the isolation structure is in direct contact with the bottom surface and sidewalls of the second part of the gate structure. A method of manufacturing the semiconductor structure includes partially etching the isolation structure to form a trench exposing the top portion of sidewalls of the substrate. The gate dielectric layer and the gate structure extend into the trench.

Abstract: Disclosed are a semiconductor sensing chip and a microfluidic sensing system. The microfluidics sensing system includes a first inlet and a second inlet, a fluidic structure, and a semiconductor sensing chip. The first inlet and the second inlet are respectively configured for injection of a sample and a reagent. The fluidic structure is coupled to the first inlet and the second inlet. The fluidic structure is configured to mix the sample and the reagent to generate a biofluid under test. The semiconductor sensing chip is disposed at the end of the fluidic structure and configured to sense the biofluidic under test and generate a concentration sensing result corresponding to the sample.

Abstract: The invention introduces an apparatus and a method for expanding round keys during data encryption. The method includes: configuring a word-processing circuitry to operate in a first mode to calculate a first intermediate calculation result corresponding to an even-number round key according to a last double word of a 0th double word to a 7th double word in each even-number clock cycle starting from a 2nd clock cycle; and configuring the word-processing circuitry to operate in a second mode to calculate a second intermediate calculation result corresponding to an odd-number round key according to the last double word of the 0th double word to the 7th double word in each odd-number clock cycle starting from a 3rd clock cycle. In the first mode, a first data path is formed in the word-processing circuitry, which includes a word split circuitry, a rotate-word circuitry, a substitute-word circuitry, a round-constant circuitry and a word concatenation circuitry.

Abstract: A method of forming a semiconductor structure includes: attaching a semiconductor device to a first surface of a substrate; placing a thermal interface material (TIM) film over a first side of the semiconductor device distal from the substrate, where the TIM film is pre-formed before the placing, where after the placing, a peripheral portion of the TIM film extends laterally beyond sidewalls of the semiconductor device; and attaching a lid to the first surface of the substrate to form an enclosed space between the lid and the substrate, where after attaching the lid, the semiconductor device and the TIM film are disposed in the enclosed space, where a first side of the TIM film distal from the substrate contacts the lid.

Abstract: There is provided a bottom cover for being covered on an optical system. The bottom cover is attached in front of the optical engine. The bottom cover has a bottom surface for facing a working surface when the optical system is moving on the working surface, a first opening for emission light of the optical engine to go through and a second opening for reflected light from the working surface to go through. The bottom cover is further formed with guiding protrusions protruded out from the bottom surface toward the working surface and surrounding at least the second opening to guide soft materials on the working surface to away from the second opening.

Abstract: A power factor correction circuit includes a first switch, a second switch, a third switch, a fourth switch, a fifth switch, a sixth switch, a seventh switch, a first inductance coil, a second inductance coil, a first capacitor, and a second capacitor. The first switch is connected to the second switch, the third switch, and the first inductance coil. The fifth switch is connected to the third switch and the second inductance coil. The sixth switch is connected to the first switch, the fourth switch, and the seventh switch. The seventh switch is further connected to the second switch, the first capacitor, and the second capacitor. The second inductance coil is further connected to the fourth switch and the first capacitor. The second capacitor is connected to the fourth switch, the sixth switch, and the first switch.

Abstract: A semiconductor structure includes a semiconductor substrate and an isolation structure disposed in the semiconductor substrate, wherein the isolation structure includes a first dielectric layer in contact with the semiconductor substrate and a second dielectric layer over the first dielectric layer, wherein the first dielectric layer is between the second dielectric layer and the semiconductor substrate, the first dielectric layer comprises a bottom portion and a sidewall portion, and a thickness of the bottom portion is greater than a thickness of the sidewall portion.

Abstract: Aspects of the present disclosure provide a method for fabricating a forksheet semiconductor structure. For example, the method can include forming on a substrate a multi-layer stack including first and second semiconductor layers stacked over one another alternately, forming a cap layer over the multi-layer stack, forming a mandrel structure from the multi-layer stack and the cap layer, forming a fill material that surrounds the mandrel structure and has a top surface level with a top of the mandrel structure, partially recessing the cap layer to uncover opposite inner sidewalls of the fill material, forming sidewall spacers on the opposite inner sidewalls, directionally etching the multi-layer stack to define an insulation wall trench using the sidewall spacers as an etch mask, and forming an insulation material within the insulation wall trench to form an insulation wall that separates the multi-layer stack into insulated first and second multi-layer stacks.

Abstract: A method for manufacturing a semiconductor device includes: forming on a substrate, a structure including a plurality of dielectric spacers and a plurality of dielectric portions that are disposed to form a plurality of recesses, such that each of the recesses is formed between a corresponding one of the dielectric spacers and a corresponding one of the dielectric portions; and subjecting the dielectric spacers and the dielectric portions to a plasma treatment process such that the dielectric spacers and the dielectric portions are deformed to form a plurality of capping portions to cap the recesses, respectively, so as to form a plurality of air gaps.

Abstract: A detecting system includes a tank unit, a pump and a controller. The tank unit includes a tank and an ultrasonic sensor. The tank stores machining fluid. The ultrasonic sensor is disposed on the tank, and measures a distance to a surface of the machining fluid stored in the tank and outputs a distance signal based on measurement of the distance. The pump is disposed on the tank, is connected to a nozzle of a machine tool, and pumps the machining fluid from the tank to the nozzle for spraying the machining fluid on a workpiece. The controller is connected to the machine tool, the ultrasonic sensor and the pump, and receives the distance signal, performs a liquid-level analysis based on the distance signal, and outputs to the machine tool a result of the liquid-level analysis.

Abstract: A method for evaluating data to be used to train an object recognition model is to be implemented by a computing device. The computing device stores a plurality of training datasets respectively related to a plurality of images, and each training dataset includes a plurality of entries of training data. The method includes steps of: obtaining, for each image, at least one target area and at least one target property that are related to the image based on the entries of training data; creating, for each image, a training material that includes the image, and the at least one target area and the at least one target property both related to the image; and obtaining at least three object recognition models based on the training materials that are created respectively for the images using at least one machine learning algorithm.