Patents by Inventor Hun Teak Lee

Hun Teak Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11145603
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: October 12, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 11024585
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: June 1, 2021
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Publication number: 20180294236
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Publication number: 20180294235
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 9997468
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 12, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 9693455
    Abstract: A system and method of manufacture of an integrated circuit packaging system includes: a copper film; a first metal layer directly on the copper film; an insulation layer directly on and over the first metal layer, the insulation layer having a via hole through the insulation layer; a conductive via within the via hole and directly on the first metal layer; a second metal layer directly on the conductive via and the insulation layer; a copper post directly on the copper film; a solder pad over the copper post; and an interposer coupled to the copper post and the solder pad.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: June 27, 2017
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Seong Won Park, Hun Teak Lee, WoonJae Beak, MinJung Kim, ChangHwan Kim, ByungHyun Kwak, GwangTae Kim, HeeSoo Lee
  • Publication number: 20160300799
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Application
    Filed: April 5, 2016
    Publication date: October 13, 2016
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 9385100
    Abstract: An integrated circuit packaging system, and a method of manufacture thereof, includes: an embedded trace substrate having bonding sites and traces embedded in a base material, an insulation layer on the traces, the insulation layer having a top surface coplanar with the top surface of the base material; and an integrated circuit die connected to the bonding sites.
    Type: Grant
    Filed: March 17, 2015
    Date of Patent: July 5, 2016
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Hun Teak Lee, YoungChul Kim, Hyunll Bae, HeeSoo Lee, HeeJo Chi
  • Patent number: 9129826
    Abstract: In a semiconductor assembly having stacked elements, discrete bumps made of a polymer such as an electrically nonconductive epoxy are interposed between the upper surface of a substrate and the lower surface of the overhanging part of an elevated element (die or package) with the discrete bump directly under bond sites on the elevated element.
    Type: Grant
    Filed: May 30, 2006
    Date of Patent: September 8, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, Chul Sik Kim, Ki Youn Jang
  • Patent number: 9093278
    Abstract: A method of manufacture of an integrated circuit packaging system including: heating a support structure having a conductive pad and an organic surface protection layer on the conductive pad; removing the organic surface protection layer from the conductive pad by a plasma process with a two-step method, the two-step method includes a first step with a dioxygen and a second step with a dihydrogen, wherein the second step immediately follows the first step; and forming an underfill over the conductive pad.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: July 28, 2015
    Assignee: STATS ChipPAC Ltd.
    Inventors: JoonYoung Choi, Seong Won Park, KyungOe Kim, Hun Teak Lee, SungWon Cho
  • Patent number: 8729687
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: May 20, 2014
    Assignee: STATS ChipPac Ltd.
    Inventors: Hun Teak Lee, Tae Keun Lee, Soo Jung Park
  • Patent number: 8716108
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: May 6, 2014
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, DaeWook Yang, Yeongbeom Ko
  • Publication number: 20130249117
    Abstract: A method of manufacture of an integrated circuit packaging system includes: providing a circuit substrate having an active side opposite to an inactive portion; attaching a nonconductive cover to the active side; forming a separation-gap partially cutting into the nonconductive cover and the circuit substrate to a kerf depth; attaching a back-grinding tape to the nonconductive cover; removing a portion of the inactive portion; and exposing the nonconductive cover by removing the back-grinding tape.
    Type: Application
    Filed: March 21, 2012
    Publication date: September 26, 2013
    Inventors: Hun Teak Lee, DaeWook Yang, Yeongbeom Ko
  • Patent number: 8519517
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: an electrical substrate having a contact pad; a support structure having a lead finger thereon; a bump on the lead finger, the bump clamped on a top and a side of the lead finger and connected with the contact pad; and an encapsulant over the lead finger and the electrical substrate.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: August 27, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Patent number: 8410594
    Abstract: An inter-stacking module system is provided by mounting an integrated circuit on a first substrate, the first substrate having a first bond pad, mounting an inter-stacking module substrate over the integrated circuit, forming an inter-stacking module bonding pad on the inter-stacking module substrate, and connecting bond wires between the inter-stacking module bonding pad and the first bond pad.
    Type: Grant
    Filed: January 11, 2006
    Date of Patent: April 2, 2013
    Assignee: Stats Chippac Ltd.
    Inventors: Kwang Soon Hwang, Youngcheol Kim, Hun Teak Lee, Koo Hong Lee
  • Publication number: 20130032954
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.
    Type: Application
    Filed: October 11, 2012
    Publication date: February 7, 2013
    Applicant: STATS CHIPPAC LTD.
    Inventors: Hun Teak Lee, Tae Keun Lee, Soo Jung Park
  • Patent number: 8304874
    Abstract: A stacked integrated circuit package-in-package system is provided including forming a first external interconnect; mounting a first integrated circuit die below the first external interconnect; stacking a second integrated circuit die over the first integrated circuit die in an offset configuration not over the first external interconnect; connecting the first integrated circuit die with the first external interconnect; and encapsulating the second integrated circuit die with the first external interconnect and the first integrated circuit die partially exposed.
    Type: Grant
    Filed: December 9, 2006
    Date of Patent: November 6, 2012
    Assignee: Stats Chippac Ltd.
    Inventors: Hun Teak Lee, Tae Keun Lee, Soo Jung Park
  • Patent number: 8269356
    Abstract: A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: September 18, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Rajendra D. Pendse, Byung Joon Han, Hun Teak Lee
  • Patent number: 8256660
    Abstract: A semiconductor package system, and method of manufacturing thereof, includes: a die having a contact pad; a lead finger having a substantially trapezoidal cross-section; a bump clamped on a top and a side of the lead finger, the bump connected to the contact pad; and an encapsulant over the lead finger and the die, the encapsulant with a bottom of the lead finger exposed.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: September 4, 2012
    Assignee: STATS ChipPAC Ltd.
    Inventors: Hun Teak Lee, Jong Kook Kim, ChulSik Kim, Ki Youn Jang
  • Patent number: 8129263
    Abstract: A method of manufacture of a semiconductor package includes: providing a substrate; mounting a semiconductor die on the substrate, the semiconductor die having a die pad; mounting a lead finger on the substrate; attaching a support pedestal on sides of the lead finger; and attaching a wire interconnection between the die pad and the support pedestal, the wire interconnection having a ball bond on the die pad and a stitch bond on the support pedestal.
    Type: Grant
    Filed: July 7, 2011
    Date of Patent: March 6, 2012
    Assignee: Chippac, Inc.
    Inventors: Hun-Teak Lee, Jong-Kook Kim, Chul-Sik Kim, Ki-Youn Jang, Rajendra D. Pendse