Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. Separate component clock signals are received by registers are brought into phase by evaluating the phases of the component clock signals at the registers, and synchronizing the component clock signal of each register to that of the previous register in a sequence.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A data system component having a state machine circuit and receivers that utilize high and low threshold signals permits accurate detection of strobe signal pattern edges such as those for preamble, burst and post-amble conditions in the strobe signal. The state machine circuit may then be configured to set conditions associated with further circuit elements such as for power saving, data reception, on-die termination, etc. based on the conditions detected in the strobe signal to improve data or memory system performance. The components may be implemented as part of memory controllers and/or memory such as a dynamic random access memory and used in memory read and write operations.

Abstract: A transmitter expresses continuous-time signals on alternate, parallel channels with reference to different supply voltages such that the signals on alternate channels have different common-mode voltages. At the transmitter, expressing the symbols using alternate supply voltages limits the maximum supply current used to express the signals and to transition between adjacent symbol sets. Limiting supply current ameliorates problems associated with simultaneous switching noise (SSN). At the receiver, the different common-mode voltages tend to balance the current to and from termination nodes, and consequently place reduced stress on a reference voltage. Providing different common-mode voltages on alternate channels may additionally reduce cross-talk between channels.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Described are amplifiers that facilitate high-speed communication with calibrated drive strength and termination impedance. Drivers and termination elements can be divided into a number N of parallel portions, one or more of which can be disabled and updated without interfering with signal (e.g., clock or data) transmission. Some embodiments identify inactive elements by examining incoming signals.

Abstract: A memory controller includes a transmit circuit coupled to an output node and a receive circuit coupled to an input node. The transmit circuit transmits first data to a memory device through the output node and the receive circuit is configured to receive second data from the memory device through the input node. The memory controller includes a calibration circuit and control logic coupled to the calibration circuit, where the calibration circuit and the control logic are configured to select a first reference voltage and a driver impedance for the transmit circuit and are configured to select a second reference voltage and a termination impedance for the receive circuit. The first reference voltage, the second reference voltage, the driver impedance and the termination impedance are selected from a set of pre-determined values, which are associated with different signaling modes for communication of the first data and the second data.

Abstract: Described are systems that employ configurable on-die termination elements that allow users to select from two or more termination topologies. One topology is programmable to support rail-to-rail or half-supply termination. Another topology selectively includes fixed or variable filter elements, thereby allowing the termination characteristics to be tuned for different levels of speed performance and power consumption. Termination voltages and impedances might also be adjusted.

Abstract: Described are on-die termination (ODT) systems and methods that facilitate high-speed communication between a driver die and a receiver die interconnected via one or more signal transmission lines. An ODT control system in accordance with one embodiment calibrates and maintains termination resistances and drive currents to produce optimal output swing voltages. Comparison circuitry employed to calibrate the reference resistance is also used to calibrate the drive current. Termination elements in some embodiments are divided into two adjustable resistive portions, both of which are designed to minimize capacitive loading. One portion is optimized to produce a relatively high range of adjustment, while the other is optimized for fine-tuning and glitch-free switching.

Abstract: Embodiments of a memory controller are described. This memory controller communicates signals to a memory device via a signal line, which can be a data signal line or a command/address signal line. Termination of the signal line is divided between an external impedance outside of the memory controller and an internal impedance within the memory controller. The memory controller does not activate the external impedance prior to communicating the signals and, therefore, does not deactivate the external impedance after communicating the signals. The internal impedance of the memory controller can be enabled or disabled in order to reduce interface power consumption. Moreover, the internal impedance may be implemented using a passive component, an active component or both. For example, the internal impedance may include either or both an on-die termination and at least one driver.

Abstract: A method of adjusting a voltage supply to an electronic device coupled to a wired communication link in accordance with a performance metric associated with the wired communication link. A voltage adjust signal is generated based on the performance metric. The voltage adjustment signal is then used for updating the voltage supply to the electronic device.