Abstract: A circuit and method for synchronized clocking of components such as registers. Registers are clocked by individual component clock signals having the same frequency but potentially different phases due to differing propagation delays. A reference clock signal is propagated along a source path and a return path, both of which pass near the registers. At each register, an averaged clock signal is generated, based on the phases of the reference clock signal on the source and return paths. Individual component clock signals are then adjusted separately to minimize differences between the component clock signals and the respective averaged clock signals at each of the registers.

Abstract: An improved, open-loop push-pull driver is described. Closed-loop feedback loop techniques for control of the push-pull driver are described. These techniques are particularly well adapted to control shoot-through current in a push-pull driver circuit.

Abstract: A phase-jumping locked loop circuit. The locked loop circuit includes a plurality of differential amplifiers and a biasing circuit switchably coupled to each of the differential amplifiers. Each of the differential amplifiers has inputs to receive a respective pair of clock signals and outputs coupled to a common pair of output signal lines. The biasing circuit comprising a first plurality of biasing transistors coupled in parallel with one another and in series with a first set of the differential amplifiers, and a second plurality of biasing transistors coupled in parallel with one another and in series with a second set of the differential amplifiers.

Abstract: A receiving unit may implement voltage compensation using a parameters table, an analog calibration component, and/or a digital calibration component. In certain implementation(s), an integrated circuit may include a voltage driver that modifies a supplied compensated voltage based on a feedback signal. The feedback signal may be produced responsive to a distributed voltage version of the compensated voltage, to a received data signal, and to a comparison involving an expected data value. In other implementation(s), a parameters table may be initialized by storing calibration values in entries in association with respective multiple identifications of multiple external points.

Abstract: An apparatus is described having a feedback loop. The feedback loop has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: An apparatus is described having a feedback loop. The feedback loop-has an output that approaches a steady state as a data line voltage approaches a reference voltage. The apparatus also includes a driving transistor that drives the data line. The driving transistor has an output impedance that is controlled by the feedback loop output, the feedback loop output keeps the driving transistor output impedance within a high output impedance region when the feedback loop output reaches the steady state.

Abstract: A differential amplifier with reduced noise sensitivity enables the bus to operate more efficiently at higher data rates. The amplifier includes an input stage with a pair of adjustable resistive loads that alter the gain of the input stage. A differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive- and negative-going voltage signals.

Abstract: A circuit for controlling signal levels on a transmission channel includes a comparator having a reference voltage input and a current control voltage input. A voltage divider is coupled to the current control voltage input of the comparator. The voltage divider includes multiple loads to divide voltages associated with a first output driver and a second output driver. The voltage divider also includes multiple switches to activate and deactivate loads in the voltage divider. A current control circuit is coupled to an output of the comparator. The current control circuit controls signal levels on the transmission channel in response to an output signal received from the comparator. Another circuit for controlling signal levels on a transmission channel includes a comparator that has a reference voltage input, a current control voltage input, and an offset control input. The offset control input is used to adjust the voltage offset on the transmission channel.

Abstract: A differential amplifier with reduced noise sensitivity enables the bus to operate more efficiently at higher data rates. The amplifier includes an input stage with a pair of adjustable resistive loads that alter the gain of the input stage. A differential output stage receives the output of the input stage and produces a pair of complementary output signals. These output signals are fed back to the adjustable resistive loads so that the gain of the input stage depends upon the levels of the output signals. The feedback is positive, so the voltage transfer characteristic of the inventive amplifier has different input thresholds for positive- and negative-going voltage signals.

Abstract: A circuit for controlling signal levels on a transmission channel includes a comparator having a reference voltage input and a current control voltage input. A voltage divider is coupled to the current control voltage input of the comparator. The voltage divider includes multiple loads to divide voltages associated with a first output driver and a second output driver. The voltage divider also includes multiple switches to activate and deactivate loads in the voltage divider. A current control circuit is coupled to an output of the comparator. The current control circuit controls signal levels on the transmission channel in response to an output signal received from the comparator. Another circuit for controlling signal levels on a transmission channel includes a comparator that has a reference voltage input, a current control voltage input, and an offset control input. The offset control input is used to adjust the voltage offset on the transmission channel.

Abstract: A differential amplifier has unequal resistance in its legs that compensates for an unequal current flow through the legs during a logic zero data input compared to logic one data input. The unequal resistance may be provided by adding a resistor in parallel to the leg that carries greater current during amplification, lowering the resistance in that leg and also the voltage that is output from that leg. Alternatively, a variable resistance may be provided to at least one of the legs to compensate for current inequalities between the legs. The variable resistance may be provided by a transistor that is controlled by a signal indicating process, voltage and/or temperature conditions of the amplifier and adjacent circuitry. Transistors may be employed in both legs as well as in a current source for the amplifier, providing balanced current regulation for the amplifier.

Abstract: A method is described that compares two voltages, one of the voltages indicative of a data line voltage, a second of the voltages indicative of a reference voltage. An input signal is sent to each of a plurality of drivers where at least one of the drivers is coupled to the data line. The input signal is based upon the comparison. A bias is applied to a transistor from the input signal, the bias keeping the transistor in a high output impedance state when the two voltages are the same.