Patents by Inventor Huy Tu

Huy Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190318755
    Abstract: Systems, methods, and computer-readable storage devices are disclosed for improved real-time audio processing. One method including: receiving audio data including a plurality of frames having a plurality of frequency bins; calculating, for each frequency bin, an approximate speech signal estimation based on the plurality of frames; calculating, for each approximate speech signal estimation, a clean speech estimation and at least one additional target including an ideal ratio mask using a trained neural network model; and calculating, for each frequency bin, a final clean speech estimation using the calculated at least one additional target including the calculated ideal ratio mask and the calculated clean speech estimation.
    Type: Application
    Filed: April 13, 2018
    Publication date: October 17, 2019
    Applicant: Microsoft Technology Licensing, LLC
    Inventors: Ivan Jelev TASHEV, Shuayb M ZARAR, Yan-Hui TU, Chin-Hui LEE, Han ZHAO
  • Publication number: 20190157442
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Application
    Filed: December 27, 2018
    Publication date: May 23, 2019
    Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Publication number: 20190128729
    Abstract: A conveyor with a weighing system includes a conveyance unit, a length calculation module, a weighing module, and a controller. The conveyance unit conveys a cargo to move. The length calculation module is arranged at one side of a front end of the conveyance unit to acquire a length of the cargo. The weighing module is arranged at a bottom part of the conveyor. The controller is connected to the length calculation module and the weighing module, such that based on the length acquired by the length calculation module, a weight of the cargo measured by the weighing module is provided. A weighing method of a conveyor is also provided.
    Type: Application
    Filed: December 21, 2017
    Publication date: May 2, 2019
    Applicant: Industrial Technology Research Institute
    Inventors: Yun-Wei Hung, Ching-Tsung Cheng, Chao-Hui Tu, Yung-Ping Tien, Yan-Ling Liao
  • Patent number: 10205014
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: December 13, 2016
    Date of Patent: February 12, 2019
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Publication number: 20180181902
    Abstract: A logistic station includes a cabinet, a storage boxes in the cabinet, a volume measurement room, a volume measurement system, a user interface and a controller. The volume measurement room has a bottom plate and a ceiling. The volume measurement system in the volume measurement room measures the volume of a consignment. The volume measurement room includes a rangefinder and an image capturing device. The rangefinder on the ceiling measures the height of the consignment placed on the bottom plate. The image capturing device is disposed on the ceiling and captures an image toward the bottom plate. The user interface disposed in the cabinet displays information and receives shipping information and a shipping fee. The controller calculates the volume information according to the image and the height, calculates the shipping fee according to the volume information and the shipping information, and controls one of the storage boxes to open.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 28, 2018
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Chao-Hui TU, Ching-Tsung CHENG, Yung-Ping TIEN, Yong-Ren LI, Wei-Syuan SYU, Yan-Ling LIAO
  • Publication number: 20180175215
    Abstract: A semiconductor device, including an insulator formed on a top surface of a semiconductor substrate, a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region, a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region, wherein the P-N junction comprises a first portion parallel to the top surface of the semiconductor substrate, and the second region is the semiconductor substrate and partially covered by the semiconductor layer, a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region
    Type: Application
    Filed: February 14, 2018
    Publication date: June 21, 2018
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Priyono Tri SULISTYANTO, Manoj KUMAR, Chia-Hao LEE, Chih-Cherng LIAO, Shang-Hui TU
  • Patent number: 9913535
    Abstract: A locker system includes a body, a driving unit, and a computer unit. The body includes a casing, a separating plate, horizontal plates, vertical plates and covering plates. The separating plate is disposed inside the casing to form an accommodating space and a storage space. The horizontal plates and the vertical plates are disposed inside the accommodating space and cooperate with the casing to form accommodating subspaces. Each covering plate is pivoted to the casing. The driving unit connects to the horizontal plates and the vertical plates. The computer unit obtains the size of an object. When the size of the object exceeds a preset size, the computer unit sends a driving signal to the driving unit, and the driving unit controls at least one horizontal plate or at least one vertical plate to move into the storage space according to the driving signal to accommodate the object.
    Type: Grant
    Filed: December 29, 2015
    Date of Patent: March 13, 2018
    Assignee: Industrial Technology Research Institute
    Inventors: Tsang-Gang Lin, Chen-Jyh Fan, Ching-Tsung Cheng, Chao-Hui Tu, Yung-Ping Tien
  • Patent number: 9705809
    Abstract: A method and device for adjusting rate of data transmission in Ethernet is provided. The method comprises: connection status of a data transmission link in the Ethernet is monitored; and a rate of data transmission in Ethernet is adjusted according to the monitored connection status. By way of monitoring the connection status of the data transmission link in Ethernet and then adjusting the rate of data transmission in Ethernet according to the monitored connection status, the problem in the related art that stability and reliability of data transmission are affected by a data transmission link failure in Ethernet is solved, thus greatly improving stability and reliability of data transmission, and improving user experience.
    Type: Grant
    Filed: September 18, 2013
    Date of Patent: July 11, 2017
    Assignee: ZTE CORPORATION
    Inventors: Wei Zhang, Dandan Guo, Xiong Tang, Jinqing Yu, Hui Tu
  • Publication number: 20170164735
    Abstract: A locker system includes a body, a driving unit, and a computer unit. The body includes a casing, a separating plate, horizontal plates, vertical plates and covering plates. The separating plate is disposed inside the casing to form an accommodating space and a storage space. The horizontal plates and the vertical plates are disposed inside the accommodating space and cooperate with the casing to form accommodating subspaces. Each covering plate is pivoted to the casing. The driving unit connects to the horizontal plates and the vertical plates. The computer unit obtains the size of an object. When the size of the object exceeds a preset size, the computer unit sends a driving signal to the driving unit, and the driving unit controls at least one horizontal plate or at least one vertical plate to move into the storage space according to the driving signal to accommodate the object.
    Type: Application
    Filed: December 29, 2015
    Publication date: June 15, 2017
    Inventors: Tsang-Gang LIN, Chen-Jyh FAN, Ching-Tsung CHENG, Chao-Hui TU, Yung-Ping TIEN
  • Patent number: 9634099
    Abstract: A lateral double diffused metal-oxide-semiconductor device includes: an epitaxial semiconductor layer disposed over a semiconductor substrate; a gate dielectric layer disposed over the epitaxial semiconductor layer; a gate stack disposed over the gate dielectric layer; a first doped region disposed in the epitaxial semiconductor layer from a first side of the gate stack; a second doped region disposed in the epitaxial semiconductor layer from a second side of the gate stack; a third doped region disposed in the first doping region; a fourth doped region disposed in the second doped region; an insulating layer covering the third doped region, the gate dielectric layer, and the gate stack; a conductive contact disposed in the insulating layer, the third doped region, the first doped region and the epitaxial semiconductor layer; and a fifth doped region disposed in the epitaxial semiconductor layer under the conductive contact.
    Type: Grant
    Filed: October 15, 2013
    Date of Patent: April 25, 2017
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung Lee, Jui-Chun Chang, Shang-Hui Tu
  • Publication number: 20170092755
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Application
    Filed: December 13, 2016
    Publication date: March 30, 2017
    Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN
  • Patent number: 9559200
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Grant
    Filed: February 24, 2016
    Date of Patent: January 31, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Chih-Jen Huang, Jui-Chun Chang, Shin-Cheng Lin, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 9553143
    Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.
    Type: Grant
    Filed: February 12, 2015
    Date of Patent: January 24, 2017
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Yu-Lung Chin, Shin-Cheng Lin
  • Patent number: 9547556
    Abstract: Methods and systems associated with re-transferring data that was unsuccessfully transmitted to a host are described. According to one embodiment a method includes transferring data from a buffer to a host; receiving an unsuccessful status from the host indicating a transmission error; identifying a block of data being transferred when the transmission error occurred; and re-transferring data in the identified block from the buffer to the host without re-transferring successfully transferred blocks.
    Type: Grant
    Filed: April 8, 2014
    Date of Patent: January 17, 2017
    Assignee: MARVELL INTERNATIONAL LTD.
    Inventors: William C. Wong, Huy Tu Nguyen, Kha Nguyen
  • Patent number: 9466730
    Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.
    Type: Grant
    Filed: January 17, 2014
    Date of Patent: October 11, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rahul Kumar, Manoj Kumar, Gene Sheu, Shao-Ming Yang, Rudy Octavius Sihombing, Chia-Hao Lee, Shang-Hui Tu
  • Patent number: 9455345
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.
    Type: Grant
    Filed: January 27, 2016
    Date of Patent: September 27, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shin-Cheng Lin, Shang-Hui Tu, Yu-Hao Ho, Wen-Hsin Lin
  • Patent number: 9443943
    Abstract: The invention provides a semiconductor device. A buried layer is formed in a substrate. A first deep trench contact structure is formed in the substrate. The first deep trench contact structure comprises a conductor and a liner layer formed on a sidewall of the conductor. A bottom surface of the first deep trench contact structure is in contact with the buried layer.
    Type: Grant
    Filed: November 12, 2014
    Date of Patent: September 13, 2016
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Geeng-Lih Lin, Kwang-Ming Lin, Shang-Hui Tu, Jui-Chun Chang
  • Patent number: 9443114
    Abstract: A system and method for verifying an identifier of a command. The method includes receiving an incoming command and sending a first alert to auto-logging hardware, wherein the auto-logging hardware sends a fetch instruction in response to receiving the first alert; retrieving an identifier of the incoming command in response to the fetch instruction and sending a second alert to the auto-logging hardware, wherein the auto-logging hardware sends a search instruction in response to receiving the second alert; and searching for the identifier of the incoming command in a table in response to the search instruction, the table storing identifiers previously assigned to other commands, wherein the incoming command is logged into the search table and marked as a searched command after the search for the first identifier in the table has completed successfully.
    Type: Grant
    Filed: February 14, 2008
    Date of Patent: September 13, 2016
    Assignee: Marvell International Ltd.
    Inventors: William C. Wong, Kha Nguyen, Huy Tu Nguyen, William W. Dennin, III, Roger Baldwin
  • Publication number: 20160240663
    Abstract: A semiconductor device includes: a semiconductor substrate; a semiconductor layer disposed over the semiconductor layer; a first well region disposed in the semiconductor layer and the semiconductor substrate; a second well region disposed in the semiconductor layer; a first isolation element disposed in the first well region; a second isolation element disposed in the second well region; a gate structure disposed in the semiconductor layer between the first isolation element and the second isolation element; a first doped region disposed in the first well region; and a second doped region disposed in the second well region. The bottom surface of the gate structure is above, below or substantially level with a bottom surface of the first isolation structure.
    Type: Application
    Filed: February 12, 2015
    Publication date: August 18, 2016
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shang-Hui TU, Yu-Lung CHIN, Shin-Cheng LIN
  • Publication number: 20160172487
    Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.
    Type: Application
    Filed: February 24, 2016
    Publication date: June 16, 2016
    Inventors: Shang-Hui TU, Chih-Jen HUANG, Jui-Chun CHANG, Shin-Cheng LIN, Yu-Hao HO, Wen-Hsin LIN