Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A charging method for a rechargeable battery and a related charging architecture are provided. The provided charging method includes following steps. A characteristic curve of the rechargeable battery related to charge cycle vs. a residual capacity of a non-constant voltage charging stage under a warranty life limitation is provided. An expected residual capacity corresponding to a condition when a terminal voltage of the rechargeable battery reaches a limited charge voltage is found from the characteristic curve related to the charge cycle vs. the residual capacity of the non-constant voltage charging stage by using a current charge cycle count of the rechargeable battery. A real residual capacity corresponding to a condition when the terminal voltage of the rechargeable battery reaches the limited charge voltage approaches to the expected residual capacity by adjusting a charging current of the rechargeable battery.

Abstract: An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A semiconductor device includes a semiconductor layer formed over a semiconductor substrate. A well region is disposed in a portion of the semiconductor layer, and a plurality of first doped regions is disposed in various portions of the well region. A second doped region is disposed in a portion of the well region. An isolation element is disposed in a portion of the top-most one of the first doped regions, and a third doped region is disposed in a portion of the top-most one of the first doped regions. A fourth doped region is disposed in a portion of the second doped region. An insulating layer overlies the third doped region, the isolation element, the second doped region, and the fourth doped region, and a conductive layer overlies the insulating layer.

Abstract: A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.

Abstract: Insulated gate bipolar transistor (IGBT) electrostatic discharge (ESD) protection devices are presented. An IGBT-ESD device includes a semiconductor substrate and patterned insulation regions disposed on the semiconductor substrate defining a first active region and a second active region. A high-V N-well is formed in the first active region of the semiconductor substrate. A P-body doped region is formed in the second active region of the semiconductor substrate, wherein the high-V N-well and the P-body doped region are separated with a predetermined distance exposing the semiconductor substrate. A P+ doped drain region is disposed in the high-V N-well. A P+ diffused region and an N+ doped source region are disposed in the P-body doped region. A gate structure is disposed on the semiconductor substrate with one end adjacent to the N+ doped source region and the other end extending over the insulation region.

Abstract: A method for estimating battery degradation is provided. In this method, a remaining capacity is obtained by looking up a device characteristic table according to a steady open circuit voltage of a battery. Besides, a constant current is provided to charge the battery, and when a terminal voltage of the battery reaches to a charging preset voltage, a constant voltage is provided to charge the battery. The transition point information at the transition from a constant current mode to a constant voltage mode, which includes a transition point estimated open circuit voltage, a transition point voltage, a transition point current and a transition point battery temperature, is analyzed based on voltage, current, temperature and capacity information measured during the charging process. A battery degradation index is calculated from the transition point information.

Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor layer formed thereover. A gate structure is disposed over the semiconductor layer, and a first doped region is disposed in the semiconductor layer adjacent to a first side of the gate structure. A second doped region is disposed in the semiconductor layer adjacent to a second side of the gate structure opposite to the first side. A third doped region is disposed in the first doped region. A fourth doped region is disposed in the second doped region. A plurality of fifth doped regions is disposed in the second doped region. A sixth doped region is disposed in the semiconductor layer under the first doped region. A conductive contact is formed in the third doped region and the first doped region.

Abstract: A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.

Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.

Abstract: The present disclosure provides a semiconductor device, including a semiconductor substrate, an epitaxial structure, a well region, a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. At least one set of first, second and third heavily doped regions formed in the well region between source and drain regions, wherein the first, second and third heavily doped regions are adjoined sequentially from bottom to top. A gate structure disposed over the epitaxial structure. The present disclosure also provides a method for manufacturing the semiconductor device.

Abstract: The invention provides a semiconductor device, including: a semiconductor device includes: a substrate having a first conductivity type, including: a body region having the first conductivity type; a source region formed in the body region; a drift region having a second conductivity type adjacent to the body region, wherein the first conductivity type is opposite to the second conductivity type; and a drain region formed in the drift region; a trench formed in the substrate between the body and drift regions; a gate dielectric layer disposed adjacent to the trench; a liner lining the trench and adjoining with the gate dielectric layer; and a gate electrode formed over the gate dielectric layer and extending into the trench.

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed on the substrate. The semiconductor device further includes a well region having a first doping concentration of a second conductivity type disposed in the epitaxial structure and the substrate. The semiconductor device further includes a drain region and a source region respectively formed in the epitaxial structure inside and outside of the well region. The semiconductor device further includes a body region of the first conductivity type disposed under the source region, and a pair of first and second doped regions disposed in the well region between the drain region and the source region. The first and second doped regions extend outside of the well region and toward the body region.

Abstract: A semiconductor device is provided. The device includes a substrate having a first conductivity type. The device further includes a drain region, a source region, and a well region disposed in the substrate. The well region is disposed between the drain region and the source region and having a second conductivity type opposite to the first conductivity type. The device further includes a plurality of doped regions disposed within the well region. The doped regions are vertically and horizontally offset from each other. Each of the doped regions includes a lower portion having the first conductivity type, and an upper portion stacked on the lower region and having the second conductivity type.

Abstract: A method and device for adjusting rate of data transmission in Ethernet is provided. The method comprises: connection status of a data transmission link in the Ethernet is monitored; and a rate of data transmission in Ethernet is adjusted according to the monitored connection status. By way of monitoring the connection status of the data transmission link in Ethernet and then adjusting the rate of data transmission in Ethernet according to the monitored connection status, the problem in the related art that stability and reliability of data transmission are affected by a data transmission link failure in Ethernet is solved, thus greatly improving stability and reliability of data transmission, and improving user experience.

Abstract: A communication system, a master device, and a communication method are provided. The communication system includes a master device and at least one slave device. The master device periodically sends a plurality of synchronous messages at intervals of a first predetermined time. The at least one slave device respectively receives the corresponding synchronous messages via wireless communication. The master device and the at least one slave device synchronously switch an operating frequency of wireless communication according to a frequency table.

Abstract: The invention provides a semiconductor device, including: a substrate of a first conductivity type having an active region and a termination region; an epitaxial layer of the first conductivity type over the substrate; a plurality of first trenches and second trenches in the epitaxial layer; an implant blocker layer formed at bottoms of the first and second trenches; a liner of a second conductivity type different from the first conductivity type conformally formed along sidewalls of the first and second trenches; a dielectric material filled in the first and second trenches defining a plurality of first columns and a plurality second column, respectively; a gate dielectric layer over the epitaxial layer; two floating gates formed on the gate dielectric layer; a source region; an inter-layer dielectric layer; and a contact plug formed on the source region.