Patents by Inventor Huy Tu

Huy Tu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20140124858
    Abstract: A semiconductor device is provided. The device includes a semiconductor substrate and a gate structure thereon. A well region is formed in the semiconductor substrate. A drain region and a source region are respectively formed in the semiconductor substrate inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. The semiconductor substrate and the first heavily doped region have a first conductivity type and the well region and the second heavily doped region have a second conductivity type. A method for fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Wen-Cheng LIN, Shang-Hui TU, Shin-Cheng LIN
  • Publication number: 20140124856
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity type, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure. A method for fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: November 7, 2012
    Publication date: May 8, 2014
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Wen-Cheng LIN, Shang-Hui TU, Shin-Cheng LIN
  • Publication number: 20140117436
    Abstract: A method for fabricating a semiconductor device is provided. An epitaxial layer is grown on a substrate, wherein the epitaxial layer and the substrate have a first conductivity type. A trench is formed in the epitaxial layer. A barrier region is formed at a bottom of the trench. A doped region of a second conductivity type is formed in the epitaxial layer and surrounds sidewalls of the trench, wherein the barrier region prevents a dopant used for forming the doped region from reaching the epitaxial layer under the barrier region. The trench is filled with a dielectric material. A pair of polysilicon gates is formed on the epitaxial layer and on both sides of the trench.
    Type: Application
    Filed: October 26, 2012
    Publication date: May 1, 2014
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Tsung-Hsiung LEE, Shang-Hui TU, Gene SHEU, Neelam AGARWAL, Karuna NIDHI, Chia-Hao LEE, Rudy Octavius SIHOMBING
  • Patent number: 8704300
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial structure of the first conductivity type disposed thereon is disclosed. A well region of a second conductivity type is formed in the epitaxial structure and the semiconductor substrate. A drain region and a source region are respectively formed in the epitaxial structure inside and outside of the well region. At least one set of the first and second heavily doped regions is formed in the well region between the drain region and the source region, wherein the first and second heavily doped regions of the first and second conductivity type, respectively, are stacked vertically from bottom to top and have a doping concentration which is larger than that of the well region. A gate structure is disposed on the epitaxial structure. A method for fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: November 7, 2012
    Date of Patent: April 22, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Wen-Cheng Lin, Shang-Hui Tu, Shin-Cheng Lin
  • Patent number: 8700966
    Abstract: Methods and systems associated with re-transferring data that was unsuccessfully transmitted to a host are described. According to one embodiment method includes receiving a first command to transfer data to a host, wherein the data is arranged in blocks. The data is transferred to the host. When an unsuccessful status is received from the host indicating a transmission error occurred for the first command, a block being transferred when the transmission error occurred is identified. The data in the identified block is re-transferred to the host without re-transferring successfully transferred blocks.
    Type: Grant
    Filed: March 25, 2013
    Date of Patent: April 15, 2014
    Assignee: Marvell International Ltd
    Inventors: William C. Wong, Huy Tu Nguyen, Kha Nguyen
  • Patent number: 8669149
    Abstract: A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.
    Type: Grant
    Filed: May 16, 2012
    Date of Patent: March 11, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Shang-Hui Tu, Hung-Shern Tsai
  • Publication number: 20140035029
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: August 2, 2012
    Publication date: February 6, 2014
    Inventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8643089
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: March 14, 2012
    Date of Patent: February 4, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8642427
    Abstract: A semiconductor device including a semiconductor substrate of a first conductivity type and an epitaxial layer of the first conductivity type disposed thereon is disclosed. Pluralities of first and second trenches are alternately arranged in the epitaxial layer. First and second doped regions of the first conductivity type are formed in the epitaxial layer and surrounding each first trench. A third doped region of a second conductivity type is formed in the epitaxial layer and surrounding each second trench. A first dopant in the first doped region has diffusivity larger than that of a second dopant in the second doped region. A method for fabricating a semiconductor device is also disclosed.
    Type: Grant
    Filed: August 2, 2012
    Date of Patent: February 4, 2014
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Rudy Octavius Sihombing, Chia-Hao Lee, Tsung-Hsiung Lee, Shang-Hui Tu
  • Patent number: 8566652
    Abstract: A method and system for command queuing in disk drives may improve performance by queuing multiple commands and sequentially executing them automatically without firmware intervention. The method may use a number of queues, e.g., a staging queue for commands to be executed, an execution queue for commands currently being executed, or a holding queue for commands which may have been executed but have not received a status report from a host.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: October 22, 2013
    Assignee: Marvell International Ltd.
    Inventors: Huy Tu Nguyen, William C Wong, Kha Nguyen, Yehua Yang
  • Patent number: 8501565
    Abstract: The invention provides a method for fabricating a deep trench isolation including: providing a substrate; forming a first trench in the substrate; conformally forming a first liner layer on the sidewall and bottom of the first trench; forming a first filler layer on the first liner layer and filling the first trench; forming an epitaxial layer on the substrate and the first trench; forming a second trench through the epitaxial layer and over the first trench; conformally forming a second liner layer on the sidewall and bottom of the second trench; and forming a second filler layer on the second liner layer and filling the second trench.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: August 6, 2013
    Assignee: Vanguard International Semiconductor Corporation
    Inventors: Yu-Lung Chin, Shang-Hui Tu, Shin-Cheng Lin
  • Publication number: 20130175607
    Abstract: A semiconductor device is provided. The semiconductor device includes a substrate having a first doping region and an overlying second doping region, wherein the first and second doping regions have a first conductivity type and wherein the second doping region has at least one first trench and at least one second trench adjacent thereto. A first epitaxial layer is disposed in the first trench and has a second conductivity type. A second epitaxial layer is disposed in the second trench and has the first conductivity type, wherein the second epitaxial layer has a doping concentration greater than that of the second doping region and less than that of the first doping region. A gate structure is disposed on the second trench. A method of fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: March 14, 2012
    Publication date: July 11, 2013
    Inventors: Tsung-Hsiung Lee, Shang-Hui Tu
  • Publication number: 20130175608
    Abstract: A semiconductor device is provided. The semiconductor device includes a plurality of first epitaxial layers, a second epitaxial layer and a gate structure. The plurality of first epitaxial layers is stacked on a substrate and has a first conductivity type. Each first epitaxial layer includes at least one first doping region and at least one second doping region adjacent thereto. The first doping region has a second conductivity and the second doping region has the first conductivity type. The second epitaxial layer is disposed on the plurality of first epitaxial layers, having the first conductivity type. The second epitaxial layer has a trench therein and a third doping region having the second conductivity type is adjacent to a sidewall of the trench. The gate structure is disposed on the second epitaxial layer above the second doping region. A method of fabricating a semiconductor device is also disclosed.
    Type: Application
    Filed: March 22, 2012
    Publication date: July 11, 2013
    Inventors: Tsung-Hsiung LEE, Shang-Hui Tu
  • Publication number: 20130149822
    Abstract: A method for fabricating a semiconductor device is provided. A method for fabricating a semiconductor device includes providing a semiconductor substrate having a first conductive type. An epitaxy layer having the first conductive type is formed on the semiconductor substrate. First trenches are formed in the epitaxy layer. First insulating liner layers are formed on sidewalls and bottoms of the first trenches. A first dopant having the first conductive type dopes the epitaxy layer from the sidewalls of the first trenches to form first doped regions. A first insulating material is filled into the first trenches. Second trenches are formed in the epitaxy layer. Second insulating liner layers are formed on sidewalls and bottoms of the second trenches. A second dopant having a second conductive type dopes the epitaxy layer from the sidewalls of the second trenches to form second doped regions.
    Type: Application
    Filed: May 4, 2012
    Publication date: June 13, 2013
    Inventors: Tsung-Hsiung LEE, Shang-Hui Tu, Rudy Octavius Sihombing
  • Patent number: 8461917
    Abstract: A complimentary single-ended-input OTA-C universal filter structures in terms of integrated circuits is provided. The integrated circuit comprises a plurality of amplifiers and a plurality of capacitors. In some capacitors, one electrode is electrically connected to the positive input of its corresponding amplifier, and the other electrode can be electrically connected to an electrical source. In addition, the negative input of one amplifier is electrically connected to the negative input of another amplifier. Besides, there are a head amplifier and a tail amplifier. The output of the head amplifier is electrically connected to the negative input of the head amplifier, and the positive input of the tail amplifier can be electrically connected to an electrical source.
    Type: Grant
    Filed: June 24, 2011
    Date of Patent: June 11, 2013
    Assignee: Chung Yuan Christian University
    Inventors: Chun-Ming Chang, Shu-Hui Tu
  • Patent number: 8412998
    Abstract: Methods and systems for performing a restart operation in a storage device include in response to receiving an unsuccessful status from the host indicating a transmission error occurred for the first command, determining in which one of the logical blocks the transmission error occurred and from which data needs to be resent, thereby identifying a restart logical block. The number of blocks in the restart logical block that were sent successfully are calculated, and it is determined that the block immediately following the blocks sent successfully is the block in which the transmission error occurred and from which the data needs to be resent, thereby identifying a restart block. An amount of data successfully sent in the restart block is determined; and an indication is provided to resend at least a portion of the data in the restart block to the host.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: April 2, 2013
    Assignee: Marvell International Ltd
    Inventors: William C. Wong, Huy Tu Nguyen, Kha Nguyen
  • Patent number: 8412895
    Abstract: The transmission of buffered data is coordinated between a storage medium and a host in response to a request from the host. One or more blocks of data are transferred from the storage medium to a buffer memory. One or more frames of data are transmitted from the buffer memory to the host, wherein the number of blocks ending in the frame is recorded in a blocks/frame register, and possibly also in a block count accumulator register. Buffer release pulses for releasing buffer space in memory are sent to the buffer memory, based on the number of blocks in the blocks/frame register, or the number of blocks accumulated in the block count accumulator register when a signal is received from the host. A pointer which points to the last block of data successfully transferred is updated in accordance with the buffer release pulses.
    Type: Grant
    Filed: February 21, 2012
    Date of Patent: April 2, 2013
    Assignee: Marvell International Ltd.
    Inventors: Huy Tu Nguyen, William C. Wong, Kha Nguyen
  • Patent number: 8358871
    Abstract: A skewed image data detecting and correcting device includes a skew angle detecting module, and an image rotating correction module. A skewed image data detecting and correcting method includes the following steps. Firstly, a binary digitizing operation is performed to obtain a binary image data. The binary image data is rotated by multiple different rotating angles, thereby obtaining multiple rotated binary image data. The pixel numbers of all horizontal rows of the rotated binary image data are totalized, thereby obtaining multiple horizontal pixel number distribution curves. A high-pass filtering procedure is performed to filter off low-frequency noise, thereby obtaining multiple high-frequency signal curves. The square sums of respective high-frequency signal curves are calculated, thereby obtaining multiple index values.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: January 22, 2013
    Assignee: AVerMedia Information, Inc.
    Inventors: Chien-Hui Tu, Cheng-Yueh Lo, De-Wei Huang, Yung-Hsi Wu
  • Patent number: 8271701
    Abstract: A FIFO memory has integrated error management to react to different errors according to the current state of operation of the input and output as well as internal conditions such as buffer memory status. The FIFO memory completes or aborts current operations according to state and leaves the FIFO memory in known condition following error handling. Thus, data sent to a host avoids data gaps or data overlaps because the FIFO memory leaves operations in a known state before reporting the error to a controller.
    Type: Grant
    Filed: May 27, 2011
    Date of Patent: September 18, 2012
    Assignee: Marvell International Ltd.
    Inventors: Huy Tu Nguyen, William C. Wong, Kha Nguyen
  • Publication number: 20120231598
    Abstract: A method for fabrication of a semiconductor device is provided. A first type doped body region is formed in a first type substrate. A first type heavily-doped region is formed in the first type doped body region. A second type well region and second type bar regions are formed in the first type substrate with the second type bar regions between the second type well region and the first type doped body region. The first type doped body region, the second type well region, and each of the second type bar regions are separated from each other by the first type substrate. The second type bar regions are inter-diffused to form a second type continuous region adjoining the second type well region. A second type heavily-doped region is formed in the second type well region.
    Type: Application
    Filed: May 16, 2012
    Publication date: September 13, 2012
    Applicant: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Shang-Hui Tu, Hung-Shern Tsai