Abstract: An electronic device includes a substrate, an active circuit, and a shielding structure. The active circuit is formed on the substrate. The shielding structure is disposed surrounding the active circuit, and includes a first heavy ion-doped region, first metal stack, second heavy ion-doped region, second metal stack and top metal. The first heavy ion-doped is formed in the substrate and located at a first side of the active circuit. The first metal stack is formed on the first heavy ion-doped region of the substrate, wherein the first metal stack is connected to a ground voltage. The second heavy ion-doped region is formed in the substrate and located at a second side of the active circuit. The second metal stack is formed on the second heavy ion-doped region of the substrate. The top metal is formed on the first metal stack and second metal stack and passing over the active circuit.

Abstract: When both the sourcing command and the sinking command to the phase comparator are high, the charge pump phase detector creates a high impedance output dead period, which is undesirable. The dead zone can be minimized by resetting the phase comparator when both sourcing command and sinking command are high. Accurate timing of the reset signal is crucial to good PLL phase noise performance and also to the elimination of the dead zone problem. In our invention, accurate reset timing is achieved by including the charge pump delay time caused by the input gate capacitance of the output complementary MOSFETs in the reset signal path.

Abstract: When both the sourcing command and the sinking command to the phase comparator are high, the charge pump phase detector creates a high impedance output dead period, which is undesirable. The dead zone can be minimized by resetting the phase comparator when both sourcing command and sinking command are high. Accurate timing of the reset signal is crucial to good PLL phase noise performance and also to the elimination of the dead zone problem. In our invention, accurate reset timing is achieved by including the charge pump delay time caused by the input gate capacitance of the output complementary MOSFETs in the reset signal path.

Abstract: Integrated fringe capacitor is structured in an IC with multi-layer metal layers sandwiched between a top metal plate and bottom plate. The multi-layers are cut into vertically aligned islands and the islands are connect series through metallized vias to either the top metal plate or the bottom metal plate. The columns connected to the top metal plate and the columns connected to the bottom metal plate are placed close to each other form the capacitor.

Abstract: The VCO of a synthesizer operates with a coarse tuning and a fine tuning. During the coarse tuning, a binary search method is used to match the VCO frequency to one of a finite number of discrete reference frequencies. The coarse tuning operates without frequency division and phase comparison in a closed feedback loop, thereby speeding up the settling time and increasing the lock-in range. The fine tuning operates as a conventional analog PLL.

Abstract: The VCO of a synthesizer operates with a coarse tuning and a fine tuning. During the coarse tuning, a binary search method is used to match the VCO frequency to one of a finite number of discrete reference frequencies. The coarse tuning operates without frequency division and phase comparison in a closed feedback loop, thereby speeding up the settling time and increasing the lock-in range. The fine tuning operates as a conventional analog PLL.

Abstract: A MOSFET operating as a mixer has its drain biased at the knee of the ID vs VDS characteristic. A local oscillator voltage is applied to the gate and a RF signal voltage is applied to the drain through a singled-ended source follower. The nonlinear curvature at the knee produces a beat frequency current. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Conversely, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain.

Abstract: A MOSFET operating as a mixer has its drain biased at the knee of the ID vs VDS characteristic. A local oscillator voltage is applied to the gate and a RF signal voltage is applied to the drain through a singled-ended source follower. The nonlinear curvature at the knee produces a beat frequency current. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Conversely, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain.

Abstract: The frequency of oscillation of two cross-coupled CMOS inverters with a parallel LC tank connected between the two drains can be varied by a control voltage which varies the capacitance value of the tank circuit. The gate-to-source capacitance is used as the variable capacitance. The gate-to-source capacitance is varied by changing the dc gate voltage, which can be effected by either changing the dc current through the inverters or by varying the dc voltage across the inverters. The control voltage may also be made to vary with temperature such that the free running frequency of the oscillator is held constant with varying temperature.

Abstract: A charge pump of a phase comparator in a phase locked loop is provided a latched comparator to minimize the effect of "dead band" during the time between charging and discharging the loop filter of the charge pump. A latch is inserted between the charging or discharging amplifier and a reset switch which turns on either the charging amplifier or the discharging amplifier. The latch speed up the change over of the charging and discharging action due to regenerative action. The latch can be an asymmetrical flip flop with one inverter fed from a reference current source and a second inverter fed from an on/off current source as controlled by the sourcing command from the phase comparator.