MOSFET mixer for low supply voltage

Abstract

A MOSFET operating as a mixer has its drain biased at the knee of the ID vs VDS characteristic. A local oscillator voltage is applied to the gate and a RF signal voltage is applied to the drain through a singled-ended source follower. The nonlinear curvature at the knee produces a beat frequency current. This mixer requires less supply voltage, and results in more conversion gain and less feed-through of the RF input signal than the Gilbert multiplier. Conversely, the RF voltage can be applied to the gate and the local oscillator voltage can be applied to the drain.

Description

[0001] This is a continuation-in-part patent application of U.S. patent application Ser. No. 09/550,638 filed Apr. 17, 2000, now abandoned.

BACKGROUND OF THE INVENTION

[0002] (1) Field of Invention

[0003] This invention relates to mixers using MOSFETs, in particular the down converter of a superheterodyne radio receiver

[0004] (2) Description of the Related Art

[0005] In a conventional radio receiver, the incoming radio frequency is mixed with a local oscillator (LO) signal to produce a beat frequency, which is the intermediate frequency (IF). The IF is then amplified and filtered to attenuate other unwanted signals,

[0006] A popular mixer circuit is the Gilbert multiplier. Since MOSFETs are widely used in circuit designs today, an MOSFET version of the Gilbert multiplier is shown in FIG. 1. Basically, a differential amplifier with a differential pair N2 and N3 is fed from a current source N1. The differential gain of the differential amplifier is proportional to the transconductance gm of N2 and N3. This transconductance varies as the square root of the dc drain current of N2 and N3, which is controlled by the drain current of N1. The dc drain current ID1of N1 is controlled by the dc gate-to-source voltage VGS1 of N1 and has a square law relationship with the gate-to-source voltage i.e. ID1OC(VGS1−Vt)2, where Vt is the threshold voltage of N1. When a local oscillator signal VLO of frequency fLO is applied differentially to N2 an N3 (i.e. VLO+ and VLO− respectively),and a radio frequency signal Vrf of frequency frf is applied to the gate of N1, the output current of the differential amplifier is equal to VLO*gm, and the gm is proportional to Vrf*(VGS1−Vt). When the Vrf is multiplied by VLO, a beat frequency fif=frf±fLO intermediate frequency signal Vif is produced.

[0007] While the Gilbert multiplier is widely used in the past, it has a number of drawbacks for low voltage and low power applications. In modern CMOS technology, the tendency is to use a low supply voltage VDD: for instance 25 V for 0.25 &mgr;m technology and 1.8 V for 0.18 &mgr;m technology. In the Gilbert mixer, the current source is operating in the current saturation region of the VDS vs ID V-I characteristic N1′ in FIG. 2 to obtain a higher transconductance and has a square law relation with Vrf. Therefore the drain voltage VDS1 for the current source N1 is larger than the knee voltage VD1′ of the N1′ V-I characteristic curve. That knee voltage VD1′ is equal to VGS1−Vt.

[0008] Similarly, the differential pair N2 and N3 also must have its drain voltage higher than the knee voltage, i.e. VD2>2(VGS1−Vt) as shown by the dotted V-I characteristic of N2 in FIG. 2. If a resistor is used as a load, another voltage drop VL will be added to VDS1 to be supplied by the power supply VDD. These three stacks of voltages, VDS1, VDS2 and VL, dictate that the supply voltage cannot be made very low. For a typical threshold voltage of 0.6 V, there is hardly any “head room” for signal voltage swing.

[0009] Lee et al disclosed in U.S. Pat. No. 6,194,947 a mixer structure which is basically a Gilbert mixer having a differential pair fed from a current source with its shortcomings.

[0010] Sakusabe disclosed in U.S. Pat. No. 5,789,963, FIGS. 1 & 9 ″, a mixer operating with a drain to source voltage VDS in the current saturation region of a MOSFET without claiming the exact VDS. The RF signal is injected to the drain of the mixer by AC coupling (i.e. through a coupling capacitor). The AC coupling requires many additional components such the coupling capacitor Ca and other components such as Z1-Z8 and capacitors C1-C5 as shown in Sakusabe's FIG. 1

[0011] Another drawback of Sakusabe's mixer is that the gate of the mixer FET2 must be adjusted to set the quiescent drain voltage to the current saturation region for different operating currents. It is desirable to set the set the quiescent operating point (i.e. VDS) automatically for different operating currents.

SUMMARY OF THE INVENTION

[0012] An object of this invention is to design a MOSFET mixer which requires a lower supply voltage than the Gilbert mixer or similar structure. Another object of this invention is to reduce the power consumption of the MOSFET mixer. Still another object of this invention is to provide a high conversion gain of the mixer. A further object of this invention is to set the operating point of the mixer at its optimum conversion gain automatically.

[0013] These objects are achieved by mixing the RF signal and the local oscillator signal at the knee of the output VDS-ID characteristic of a MOSFET by dc coupling. At the knee, the characteristic has the sharpest curvature. The nonlinearity produces a maximum beat frequency signal. For implementation, a mixer MOSFET is biased at the knee of the VDS-ID characteristic. The LO (or RF) signal voltage VLO (or Vrf) is applied at the gate of the mixer MOSFET, and the RF (or LO) signal voltage Vrf(or VLO) is injected at the drain of the mixer MOSFET. Then a beat frequency drain current is produced. Specifically, the gate of a single-ended mixer MOSFET is fed with a local oscillator signal and the drain of the mixer is dc coupled to a single-ended source follower with the gate fed from a radio frequency signal or vise versa.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0014] FIG. 1 shows a prior art Gilbert mixer.

[0015] FIG. 2 shows the output V-I characteristic of MOSFETs.

[0016] FIG. 3 shows the basic circuit of the present invention.

[0017] FIG. 4 shows the basic circuit with an inductive load.

[0018] FIG. 5 shows a dc biasing circuit for automatically biasing the mixer MOSFET to the drain knee voltage.

DETAILED DESCRIPTION OF THE INVENTION

[0019] The basic circuit of the present invention is shown in FIG. 3. Two N-channel MOSFETs N2′ and N1′ are connected in series. The pull-down NMOS N1′ has its source grounded and its drain D1 connected to the source of the pull-up NMOS N2. The drain D2 of N2′ is connected through a load RL to the positive power supply VDD. The RF voltage Vrf is applied to the gate of N1′, which has a dc bias voltage VG1. The drain D1 of the N1′ is set at a quiescent voltage Vknee at the knee of the VDS-ID characteristic of N1′. This voltage is Vknee=(VG1−Vt), where Vt is the threshold voltage of N1′. The appropriate Vknee is set by choosing the appropriate dc gate voltage VG2 of N2′.

[0020] A LO signal voltage VLO is applied to the gate of N2′, and an RF voltage is applied to the gate of N1′. At the knee of the VDS-ID characteristic of N1′, the dc current:

ID=(K/2)[2(VGS−Vt)VDS−VDS2]  (1)

[0021] where K is a transconductance parameter

[0022] The slope is:

&Dgr;ID/&Dgr;VDS=K(VGS−Vt−VDS)  (2)

[0023] Let a sine wave RF signal Vrf sin &ohgr;rft be applied to the gate of N1′ and a sine wave LO signal VLO sin &ohgr;LOt be applied to the gate of N2′. Due to source follower action, &Dgr;VDS=VLO sin &ohgr;LOt. Then equation (2) can be written as:

&Dgr;ID=K[(VGS+Vrf sin &ohgr;rft)−Vt−VDS]VLO sin &ohgr;LOt=KVLO sin &ohgr;LO t*Vrf sin &ohgr;rft+K(VGS−Vt−VDS)*VLO sin &ohgr;LOt  (3)

[0024] The first term on the right side of equation (3) is a cross product term which yields a beat frequency signal Vif

[0025]   Vif=KVLOVrf[ cos (&ohgr;rf−&ohgr;LO)t]/2  (4)

[0026] The sum frequency KVLOVrf[ cos (&ohgr;rf+&ohgr;LO)t]/2 term in equation (3) can be filtered out in the IF amplifier. The dc term (VGS−Vt−VDS) is equal to zero at the knee.

[0027] The foregoing analysis also holds true if the local oscillator voltage VLO and the RF voltage Vrf are interchanged.

[0028] For comparison with the Gilbert multiplier, it is assumed that ID1 is the same in both cases, and all three MOSFETs N1, N2 and N3 in the Gilbert mixer as shown in FIG. 1 are the same. Then, the dc currents ID2=ID3=ID1/2. The ac differential output current is:

Id2=2gm2*VLO/2  (5)

[0029] where gm2 is the transconductance of N2 and

gm2=(2K ID2)½=(KID1)½  (6)

[0030] Combining (5) and (6), the ac output current becomes: Id2=VLO(KID1)½  (7)

[0031] With the RFvoltage Vg1 at the gate of N1,

ID1=K(VGS1+Vg1−Vt)2/2  (8)

[0032] Let Vg1=Vrf sin &ohgr;rft and VLO(t)=VLO sin &ohgr;LOt  (9)

[0033] Combine equations (7), (8) and (9)

Id2=K VLOf sin &ohgr;LOt*(Vrf sin &ohgr;rft+VGS1−Vt)/2½  (10)

[0034] Note that the cross product term KVrf sin &ohgr;rft*VLO sin &ohgr;LOt/2½ of equation (10) is ½½ that of the cross product in equation (3). Therefore the present invention shown in FIG. 3 has 2½ times the conversion gain of the Gilbert mixer.

[0035] In addition, the present invention has the advantage of a lower VDS1=VGS1−Vt, while the Gilbert mixer must use a VDS1>VGS1−Vt. Furthermore, the Gilbert's differential pair must be operating in the current saturation region to obtain high transconductance, i.e. N2 and N3 also require high drain voltage VDS2>VGS2−Vt. On the other hand, N2′ of the present invention acts like a transmission gate, and the dc drain to source voltage VDS2′ is equal to the voltage drop across the on resistance Ron of N2′. This voltage drop VDS2′(≈ID2′Ron) [is] can be less than (VGS2′−Vt) as shown by the load line of N2′ in FIG. 2 and can be made low by reducing Ron (i.e. large width to length ratio of the gate of N2′). This reduction in VDS1′ and VDS2′ for FIG. 3 translates into a lower supply voltage VDD, as indicted by VD2(min) for the Gilbert mixer and VD2′ for the present invention. The characteristic of N2′ in FIG. 2 assumes that N2′ is twice as wide as N1′ and equal to the total width of N2 and N3 of the Gilbert mixer.

[0036] Note also the RF component Vrf sin &ohgr;rft(VGS1−Vt−VDS) in equation (3) for the present invention is equal to zero, because (VGS1−Vt−VDS) is equal to zero at the knee. Conversely in equation (10) for the Gilbert mixer, the RF component Vrf sin &ohgr;rft(VGS1−Vt) is not equal to zero, and must be filtered out to avoid intermodulation. On the other hand, , the RF component in the present invention is equal to zero and need not be filtered. The elimination of filtering the RF component is an advantage. Although the image frequency (&ohgr;rf+&ohgr;LO) is still present, this frequency is far away from the beat frequency (&ohgr;rf−&ohgr;LO) and can be filtered out more easily than the lower RF signal &ohgr;rf. Thus, there is less feed-through of the input RF signal for the present invention than the Gilbert mixer, and the ratio of the magnitudes of the image frequency to the beat frequency is no worse than the Gilbert mixer.

[0037] In the foregoing analysis, it is assumed that the RF signal Vrf is applied to the gate of N1′ and the local oscillator voltage VLO is applied to the gate of N2′. From equation (4), the beat frequency IF voltage is proportional the product Vrf*VLO. Therefore, from a theoretical standpoint where the voltage gain the source follower N2′ is assumed to be unity, the conversion gain should be the same when VLO is applied to N1′ and Vrf is applied to N2′. In practice, however, the gain of the source follower N2′ is less than unity. When Vrf is applied to the gate of N2′, the RF signal at the source of N2′ is less than the signal at the gate. In either case, the noise output should be the same. As a result, the signal-to-noise ratio at the output of the mixer can be better for the case where the RF signal is applied to N1′ and the local oscillator voltage is applied to N2′.

[0038] While the load device shown in FIG. 3 is a resistor with a voltage drop, the power supply voltage VDD can further be reduced by using an inductive load device as shown in FIG. 4. The inductance L can be connected in parallel with a capacitor to form a tank circuit resonant at the beat or intermediate frequency fif.

[0039] Besides the lower supply voltage and reduced RF feedthrough, the single-ended mixer of the present invention also has some other advantages over the balanced structure of the Gilbert circuit. A balanced structure requires differential RF and LO inputs and IF outputs. Most applications only provide single-ended RF and LO inputs and preferably single-ended IF output. As a result, the user need to provide single-to differential buffer amplifiers for RF and LO, and differential-to-single-ended buffer for the IF. Otherwise, differential filters are needed. Buffer amplifiers consume power while differential filters cost more and sometimes not available.

[0040] In the present invention, the dc knee voltage Vknee of the first mixer MOSFET N1′, VG1−Vt, is equal to the dc source voltage VS2 of the source follower N2′, i.e. VS2=VG1−Vt. For equal size N1′ and N2′ and equal source currents and VD2≧VG2−Vt, VG1−Vt=VG2−VS2−Vt. Combining these relations yields

VG2=2VGS1−Vt.  (11)

[0041] So long as this relationship is satisfied, the mixer N1′ is automatically biased to the knee without adjustment, regardless of the drain or source current of the mixer MOSFET N1′. FIG. 5 shows a circuit for satisfying this dc requirement. In this circuit, the supply voltage VG2 is divided into one half by a voltage divider of two equal R1+R2. The divided voltage VG2/2 is added with a divided threshold voltage Vt/2 across the MOSFET N4 in diode connection, which has a threshold voltage Vt from drain to source, to constitute the dc gate bias VG1. The dc drain voltage VD2 can be lower than (VG2−Vt) as explained previously. As can be seen from FIG. 5, only a low supply voltage VG2 less than twice the VG1 is needed. The RF voltage and local oscillator voltage can readily be superimposed on VG1 and VG2 (not shown). For unequal size N1′ and N2′, another condition similar to eq.(11) can be derived as as follows: VG2=[1+{square root}(K1/K2)] VG1−[{square root}(K1/K2)]Vt  (12)

[0042] where K1 and K2 are the transconductance parameters as defined in eq.(1).

[0043] VG2 is the minimum dc supply voltage required to operate the present invention, and is compared favorably to the Gilbert mixer, because the dc drain voltage of N2 or N3 used for the Gilbert mixer shown in FIG. 1 requires a higher drain voltage than (VG2−Vt) for proper operation of N2 and N3 in the current saturation region, the dc drain voltage of N1 requires a higher dc drain voltage than N1′ for proper operation in the current saturation region, and the load R connected to VDD requires additional voltage drop. Thus the required dc voltage supply VDD for the Gilbert mixer is much higher than the dc supply voltage of the present invention. If VG2 is used as the supply voltage VDD for N2′ and the dc drain voltage VD2 of N2′ need only be less than (VG2−Vt), then a large load as shown in FIG. 3 can be inserted between VDD and VD2 to obtain more conversion gain. More importantly, the present invention has a higher conversion gain than the Gilbert mixer.

[0044] While the forgoing mixer is described using MOSFETs, similar technique should be applicable to bipolar transistors.

[0045] While the preferred embodiments of this invention have been described, it will be apparent to those skilled in the art that various modifications may be made in the embodiments without departing from the spirit of the present invention. Such modifications are all within the scope of this invention.

Claims

1. A mixer circuit using MOS field effect transistors (MOSFET) having a threshold voltage Vth, a drain characteristic with an ohmic region where the drain current ID increases with increasing drain-to-source voltage VDS, and current saturation region where the drain current is constant with increasing VDS for a fixed gate-to-source voltage, comprising:

a first MOSFET having a first source, a first gate and a first drain;

a ground supply voltage applied to said first source;

a first dc quiescent gate voltage applied to said first gate;

a first radio frequency (RF) voltage V1 superimposed on said first dc quiescent gate voltage;

a second MOSFET operating as a single ended source follower, having a drain connected to a dc power supply, a source dc-connected to to said first drain of said first MOSFET, and a gate: applied with a dc gate voltage such that the dc drain-to-source voltage of the said first MOSFET is equal to a transition (knee) voltage Vknee between said ohmic region and said current saturation region below said current saturation region of the drain characteristic of the said first MOSFET, and superimposed with a second RF voltage V2; and

a means to sense the drain current of said second MOSFET having a frequency component equal the beat frequency of said V1 and said V2.

2. The mixer circuit as described in

claim 1, wherein said Vknee is equal to said dc quiescent gate voltage minus said threshold voltage.

3. The mixer circuit as described in

claim 1, wherein said means to sense is a resistor.

4. The mixer circuit as described in

claim 1, wherein said means to sense is an inductor.

5. The mixer circuit as described in

claim 4 further comprising a capacitor in parallel with aid inductor to form a parallel resonant circuit, resonant at said beat frequency.

6. The mixer circuit as described in

claim 1, wherein said first MOSFET and said second MOSFET are N-channel field effect transistors and said dc supply voltage is positive.

7. A mixer circuit as describe in

claim 1, wherein said means to sense is a current meter.

8. A mixer circuit as described in

claim 1, wherein said first RF voltage is an incoming signal voltage and said second RF voltage is a local oscillator voltage of a superheterodyne radio receiver.

9. A mixer circuit as described in

claim 1, wherein said second RF signal is an incoming signal voltage and said first RF signal is a local oscillator voltage of a superheterodyne receiver.

10. A mixer circuit as described in

claim 1, wherein the first MOSFET and the second MOSFET are of equal size, the dc drain voltage of the second MOSFET is at least one threshold voltage less than the dc gate voltage, and the dc gate voltage of said second MOSFET is equal to twice the dc gate-to-source of said first MOSFET minus the threshold voltage (Vt) of said second MOSFET so that the dc drain-to-source voltage of said first MOSFET is automatically biased to the Vknee.

11. A mixer circuit as described in

claim 10, wherein the dc gate-to-source of said first MOSFET is obtained by dividing the dc gate supply voltage of said second MOSFET into one half and adding one half of a threshold voltage.

12. A mixer circuit as described in

claim 1, wherein the first MOSFET and second MOSFET are of equal size, the dc drain voltage of the second MOSFET is at least one threshold volage less than the de gate voltage, and the dc gate voltage of said second MOSFET is equal to [1+{square root}(K1/K2)] times the de gate voltage of said first MOSFET minus ({square root}(K1+K2) times the threshold voltage of said second MOSFET, where K1 and K2 are the transconductance parameters of the first MOSFET and the second MOSFET, respectively, so that the dc drain-to-source voltage of said first MOSFET is automatically biased the knee voltage Vknee.