Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A termination circuit includes: a pull-up termination unit configured to pull-up terminate an interface node in response to a pull-up signal; a pull-down termination unit configured to pull-down terminate the interface node in response to a pull-down signal; one or more pull-up resistors connected to the interface node and enabled to affect termination resistance in response to a pull-up setting value when a termination signal is activated; and one or more pull-down resistors connected to the interface node and enabled to affect termination resistance in response to a pull-down setting value when the termination signal is activated.

Abstract: A semiconductor device includes: a main driving unit configured to receive an output data and to drive the received data to a data output pad; a pre-emphasis data generation unit configured to compare a delayed data obtained by delaying the output data by one data period with the output data, to delay the comparison result by one data period, and to output the delayed data as pre-emphasis data; and a pre-emphasis driving unit configured to receive the pre-emphasis data and to drive the received data to the data output pad.

Abstract: A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.

Abstract: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to generate at least one strobe signal in response to the clock signal, and to adjust transition timings of the strobe signal in response to the timing control signals.

Abstract: A semiconductor integrated circuit includes an impedance control signal generation block configured to transmit first impedance control signals and second impedance control signals through same signal lines at predetermined time intervals, and input/output blocks configured to separately receive the first impedance control signals and the second impedance control signals at corresponding time intervals and perform a data input/output operation based on set impedance.

Abstract: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.

Abstract: An apparatus for generating an output data strobe signal include a timing control unit configured to detect a specific data pattern and to generate a plurality of timing control signals corresponding to the detected data pattern in response to a clock signal; and a strobe signal generating unit configured to generate at least one strobe signal in response to the clock signal, and to adjust transition timings of the strobe signal in response to the timing control signals.

Abstract: Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups and then outputs data to the pads from the other of the first and second bank groups.

Abstract: An output driver for use in a semiconductor device includes a first pre-drive unit, a second pre-drive unit, and a main drive unit. The first pre-drive unit generates a pull-up drive control signal based on a data signal. The pull-up drive control signal swings between a power supply voltage level and a low voltage level. The data signal swings between the power supply voltage level and a ground voltage level. The second pre-drive unit generates a pull-down drive control signal based on the data signal. The pull-down drive control signal swings between a high voltage level and the ground voltage level. The main drive unit performs pull-up/down drive operations to an output terminal in response to the pull-up/down drive control signals, respectively. Herein, the high voltage level is higher than the power supply voltage level and the low voltage level is lower than the ground voltage level.

Abstract: An output driver for use in a semiconductor device includes a first pre-drive unit, a second pre-drive unit, and a main drive unit. The first pre-drive unit generates a pull-up drive control signal based on a data signal. The pull-up drive control signal swings between a power supply voltage level and a low voltage level. The data signal swings between the power supply voltage level and a ground voltage level. The second pre-drive unit generates a pull-down drive control signal based on the data signal. The pull-down drive control signal swings between a high voltage level and the ground voltage level. The main drive unit performs pull-up/down drive operations to an output terminal in response to the pull-up/down drive control signals, respectively. Herein, the high voltage level is higher than the power supply voltage level and the low voltage level is lower than the ground voltage level.

Abstract: A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines, for synchronizing time that the plurality of data transferred through the respective data lines take to arrive at the receiver.

Abstract: A semiconductor memory device includes a semiconductor circuit substrate having a chip pad forming region. A pair of data lines are formed on the semiconductor circuit substrate at one side of the chip pad region. The pair of data lines extend along a direction that the chip pad region of the semiconductor circuit substrate extends. The pair of data lines are arranged to be adjacent to each other and receive a pair of differential data signals. A power supply line is formed on the semiconductor circuit substrate at the other side of the chip pad region. The power supply line extends along the direction that the chip pad region of the semiconductor circuit substrate extends, and the power supply line receives power.

Abstract: A semiconductor memory apparatus includes a write driver that receives data transmitted through an input/output line, and a synchronous delay circuit unit that generates an enable signal so as to allow the data transmitted through the input/output line to be supplied to the write driver.

Abstract: A semiconductor memory device including a plurality of banks, each including a plurality of memory cells, a pattern signal generator configured to generate pattern signals having combinations in response to an input signal applied through an arbitrary pad in a compression test mode. Input paths are configured to transfer the plurality of pattern signals to the corresponding banks.

Abstract: There is provided a signal transfer circuit, comprising a first pull-up transistor and a first pull-down transistor configured to drive a first signal transmission line in response to a signal of a second signal transmission line, a first path controlling unit configured to prevent a signal from being transferred through a first path by controlling a gate of the first pull-up transistor and a gate of the first pull-down transistor when a first path enable signal is deactivated, a second pull-up transistor and a second pull-down transistor configured to drive the second signal transmission line in response to a signal of the first signal transmission line, and a second path controlling unit configured to prevent a signal from being transferred through a second path by controlling a gate of the second pull-up transistor and a gate of the second pull-down transistor when a second path enable signal is deactivated.

Abstract: A semiconductor memory apparatus includes a write driver that receives data transmitted through an input/output line, and a synchronous delay circuit unit that generates an enable signal so as to allow the data transmitted through the input/output line to be supplied to the write driver.

Abstract: Disclosed is a test mode control apparatus of a semiconductor memory having a plurality of banks divided into first and second bank groups, a plurality of pads, and a test mode controller. The test mode controller outputs data to the pads from one of the first and second bank groups and then outputs data to the pads from the other of the first and second bank groups.