Abstract: A semiconductor memory device performs a data-compress test under the same conditions as a normal mode. The semiconductor memory device includes a cell bank for including plural memory cell units for data storage and a data sense amplifying block for sensing and amplifying plural output data of the cell bank and for outputting the data through plural global lines, a compressor, coupled to the data sense amplifying block, for compressing the data transferred through the plural global lines and outputting one-bit compress-data, and data output units for storing the data transferred through the plural of global lines or the compress-data selectively and outputting the data externally.

Abstract: A semiconductor device is capable of minimizing data skew among respective data which are transmitted to a receiver through respective data lines. The semiconductor device includes a synchronization unit connected to at least one portion of the respective data lines, for synchronizing time that the plurality of data transferred through the respective data lines take to arrive at the receiver.

Abstract: Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from being occurred. The semiconductor memory device, which comprises a data inputting block 30 for transferring data applied to a plurality of data input/output pins DQ0 to DQ15 to a plurality of global I/O buses gio<0:15>, a data multiplexing block 32 for multiplexing the data carried on the plurality of global I/O buses gio<0:15> according to a data width option, and a main write driver 34, in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.

Abstract: A semiconductor memory device including a read and a write structures are provided. The read structure includes: a core sense amplifier part for amplifying data applied on data buses of a core area; a read multiplexing part for multiplexing the output data of the core sense amplifier part according to data width options and transferring the multiplexed data to a peripheral area through data buses; and a data output part for transferring the data of the data buses to a plurality of data I/O pins. The write structure includes: a data input part for transferring data applied on a plurality of data I/O pins to a core area through data buses; a write multiplexing part for multiplexing the data of the data buses according to data width options; and a core driver part for driving the output data of the write multiplexing part to data buses of the core area.

Abstract: A semiconductor memory device including a read and a write structures are provided. The read structure includes: a core sense amplifier part for amplifying data applied on data buses of a core area; a read multiplexing part for multiplexing the output data of the core sense amplifier part according to data width options and transferring the multiplexed data to a peripheral area through data buses; and a data output part for transferring the data of the data buses to a plurality of data I/O pins. The write structure includes: a data input part for transferring data applied on a plurality of data I/O pins to a core area through data buses; a write multiplexing part for multiplexing the data of the data buses according to data width options; and a core driver part for driving the output data of the write multiplexing part to data buses of the core area.

Abstract: Provided is a semiconductor memory device, which is capable of further simplifying the data multiplexing structure on a data write path, thereby preventing a timing mismatch in data input from being occurred. The semiconductor memory device, which comprises a data inputting block 30 for transferring data applied to a plurality of data input/output pins DQ0 to DQ15 to a plurality of global I/O buses gio<0:15>, a data multiplexing block 32 for multiplexing the data carried on the plurality of global I/O buses gio<0:15> according to a data width option, and a main write driver 34, in response to a control signal, for driving the data outputted from the multiplexing means to a memory core region.