Abstract: A manufacturing method of a liquid crystal display includes: forming an etch target layer including a conductive material on a first substrate; forming a first mask layer on the etch target layer; forming a block copolymer coating layer including a plurality of polymers on the first mask layer; processing the block copolymer coating layer to form a block copolymer pattern layer including first and second polymer blocks; removing one of the first or second polymer blocks to form a second mask pattern layer; etching the first mask layer by using the second mask pattern layer as an etching mask to form a first mask pattern layer; and etching the etch target layer by using the first mask pattern layer as an etching mask to form a first electrode. The first electrode includes a plurality of the first minute patterns extending in a predetermined direction and having a polarization function.

Abstract: A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: A thin film transistor array panel includes: a substrate, a plurality of gate and data lines, a thin film transistor, a light blocking member, a color filter, and a pixel electrode. The substrate includes a display area having a plurality of pixels and a non-display area. The gate lines and data lines are formed on the substrate. The thin film transistor is connected to a respective gate line and data line of the plurality of gate and data lines. The light blocking member is formed on the non-display area, the gate line, the data line, and the thin film transistor. The color filter is formed on the light blocking member. The pixel electrode is formed on the color filter. The color filter covers the entire light blocking member of the non-display area.

Abstract: A TFT array panel includes an insulating substrate, a gate line, a storage electrode line, a gate insulating layer, a semiconductor island formed on the gate insulating layer, and a data line and a drain electrode formed thereon. The data line and drain electrode are covered with a passivation layer. A pixel electrode is formed on the passivation layer and connected to the drain electrode through a contact hole. The TFT array panel is covered with an alignment layer rubbed approximately in a direction from the upper left corner to lower right corner of the TFT array panel or the pixel electrodes. The pixel electrode overlaps the gate line and data line and has an expansion located near the upper left corner of the pixel electrode to increase the width of the corresponding overlapping area between the pixel electrode and the gate line and/or data line.

Abstract: A photomask includes a substrate, a mask pattern layer and a super lens. The substrate includes a pattern which includes protruding portions, and open portions between the protruding portions. The mask pattern layer is in the open portions of the pattern and fills the open portions of the pattern. The super lens is on the substrate and the mask pattern layer.

Abstract: A display substrate includes a pixel switching element, a pixel electrode, a reference line, a control switching element, a bias line, a light sensing element, a sensing capacitor and a light blocking filter pattern. The pixel switching element is connected to a data line and a gate line, includes a first semiconductor pattern. The pixel electrode is connected to the pixel switching element. The reference line is in parallel with the data line. The control switching element is connected to the reference line and the gate line, includes a second semiconductor pattern. The bias line is in parallel with the gate line. The light sensing element is connected to the bias line and the control switching element, includes a third semiconductor pattern. The sensing capacitor is connected to the light sensing element and a storage line. The light blocking filter pattern transmits a first light, and blocks a second light.

Abstract: A thin-film transistor (TFT) substrate includes a semiconductor pattern, a conductive pattern, a first wiring pattern, an insulation pattern and a second wiring pattern. The semiconductor pattern is formed on a substrate. The conductive pattern is formed as a layer identical to the semiconductor pattern on the substrate. The first wiring pattern is formed on the semiconductor pattern. The first wiring pattern includes a source electrode and a drain electrode spaced apart from the source electrode. The insulation pattern is formed on the substrate having the first wiring pattern to cover the first wiring pattern. The second wiring pattern is formed on the insulation pattern. The second wiring pattern includes a gate electrode formed on the source and drain electrodes. Therefore, a TFT substrate is manufactured using two or three masks, so that manufacturing costs may be decreased.

Abstract: A liquid crystal display includes a first insulating substrate including a display area and a peripheral area, a display area signal line in the display area of the first insulating substrate.

Abstract: A TFT array panel includes a substrate, a first gate line and a second gate line disposed on the substrate, a storage electrode line disposed on the substrate, a first data line intersecting the first and second gate lines, a second data line intersecting the first and second gate lines and spaced apart from the first data line, a drain electrode facing a part of the first data line and the second data line, an organic insulating layer disposed on the first data line and the second data line, the organic insulating layer having a contact hole exposing the drain electrode, a pixel electrode disposed on the organic insulating layer, the pixel electrode electrically connected to the drain electrode, and a storage electrode making a storage conductor with the pixel electrode, wherein the pixel electrode comprises a first part overlapping the first data line, and a second part overlapping the second data line, and wherein the width of the first part is different from that of the second part.

Abstract: A liquid crystal display includes first and second gate lines, a data line crossing the first and second gate lines, a pixel electrode including first and second sub-pixel electrodes electrically disconnected from each other, a first thin film transistor connected to the first gate line, the data line, and the first sub-pixel electrode, a second thin film transistor connected to the first gate line, the data line, and the second sub-pixel electrode, and a third thin film transistor connected to the second gate line, the second sub-pixel electrode, and a charge sharing capacitor including a first and second electrode. A data voltage applied to the second sub-pixel electrode and to a first electrode swings between a negative voltage and a positive voltage with respect to a common voltage, and a voltage smaller than an average value of the negative voltage and the positive voltage is applied to a second electrode.

Abstract: A display substrate includes a transistor layer, a plurality of color filters, a first blocking member, a supporting member, a circuit part, a second blocking member and a protruding member. The first blocking member is disposed between different color filters. The supporting member maintains a distance between a base substrate and a substrate facing the base substrate. A circuit part is disposed in a peripheral area surrounding a display area, and the circuit part includes a metal pattern and a contact electrode in contact with the metal pattern. The second blocking member includes substantially the same material as the first blocking member and the second blocking member covers the circuit part. The protruding member includes substantially the same material as the second blocking member, and is integrally formed with the second blocking member.

Abstract: An array substrate includes a substrate including a display area and a peripheral area surrounding the display area, a transistor layer formed in the display area of the substrate and electrically connected to a gate line and a data line, a color filter formed in a pixel region on the transistor layer, a first light blocking member disposed between adjacent color filters, a first transparent member formed on the first light blocking member to cover the first light blocking member, a first color pattern formed in a peripheral area of the substrate and including substantially the same material as the color filter, and a second transparent member including substantially the same material as the first transparent member. The second transparent member is disposed in the peripheral area of the substrate to cover the first color pattern.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: Contamination is blocked from material of a color filter layer provided on a thin-film transistors (TFT) supporting substrate by sealing over the color filter layer with an inorganic insulating layer. During mass production manufacture, a plasma surface cleaning step is employed after the color filter layer is deposited but before the inorganic insulating layer is deposited. A low temperature CVD process is used to deposit the inorganic insulating layer with a substantially uniform thickness conformably over the color filter layer including conformably into openings provided through the color filter layer.

Abstract: A first wiring is formed on an array substrate, such that the first wiring has a first protrusion. A second wiring is formed on a different layer from that of the first wiring, such that a portion of the second wiring overlaps with the first protrusion. A protection layer that covers the first and second wirings is formed, such that the protection layer has first and second contact holes that expose the first and second wirings, respectively. Then, a third wiring that electrically connects the first wiring to the second wiring through the first and second contact holes is formed. When electrical connection between the first and second wirings is abnormal, a laser beam is irradiated toward the first protrusion, so that the electrical connection may be repaired.

Abstract: Provided are a thin-film transistor (TFT) substrate which can facilitate the formation of contact holes and has improved reliability and a method of fabricating the TFT substrate. The TFT substrate includes a gate wiring formed on an insulating substrate; a data wiring defining a pixel region by intersecting the gate wiring, the data wiring including a source electrode and a drain electrode; a plurality of black matrix barrier ribs formed along the boundaries of the pixel region; a color filter formed to cover the pixel region; a pixel electrode formed on the color filter; and a plurality of contact holes formed through the color filter near the corners of the pixel region through which the pixel electrode and the drain electrode contact each other.

Abstract: A thin film transistor array panel including a substrate; a display area signal line; a display area thin film transistor; a peripheral area signal line; a black matrix disposed on the display area signal line, the display area thin film transistor, and the peripheral area signal line, the black matrix including a first and a second contact holes exposing the peripheral area signal line; a protrusion member disposed on the peripheral area signal line, the protrusion member overlapping the peripheral area signal line; a transparent connector disposed on the black matrix and within the peripheral area, wherein the transparent connector contacts the peripheral area signal line through at least one of the first and the second contact holes and includes a protrusion within at least one of the first and the second contact holes which corresponds to the protrusion member; and a pixel electrode.

Abstract: Contamination is blocked from material of a color filter layer provided on a thin-film transistors (TFT) supporting substrate by sealing over the color filter layer with an inorganic insulating layer. During mass production manufacture, a plasma surface cleaning step is employed after the color filter layer is deposited but before the inorganic insulating layer is deposited. A low temperature CVD process is used to deposit the inorganic insulating layer with a substantially uniform thickness conformably over the color filter layer including conformably into openings provided through the color filter layer.

Abstract: A thin film transistor array panel is provided, which includes: a gate line, a gate insulating layer, and a semiconductor layer sequentially formed on a substrate; a data line and a drain electrode formed at least on the semiconductor layer; a first passivation layer formed on the data line and the drain electrode and having a first contact hole exposing the drain electrode at least in part; a second passivation layer formed on the first passivation layer and having a second contact hole that is disposed on the first contact hole and has a first bottom edge placed outside the first contact hole and a second bottom edge placed inside the first contact hole; and a pixel electrode formed on the second passivation layer and connected to the drain electrode through the first and the second contact holes.