Abstract: An array substrate (100a) includes a transparent substrate (304), a first insulation layer (306) and a pixel electrode (103). The transparent substrate (304) includes a display region (DR) that displays an image, a peripheral region (PR) having a driving circuit (101) for displaying an image through the display region, and a sealine region (SLR) that surrounds the display region (DR) to define the display region and the peripheral region (PR). The first insulation layer (306) is formed over the transparent substrate (304), and the first insulation layer (306) has an opening window (301) in the sealine region (SLR). The pixel electrode (103) is formed on the first insulation layer (306) of the display region (DR). The bonding between a color filter substrate (401) and an array substrate (100a) is improved. Furthermore, liquid crystal material is completely filled into between the color filter substrate and the array substrate.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A thin film transistor array panel and a method of its manufacture are presented. The thin film transistor array panel according to an embodiment includes a substrate, a gate line extending in a first direction on the substrate, a data line extending in a second direction on the substrate and intersecting and insulated from the gate line, a thin film transistor including a control terminal connected to the gate line, an input terminal connected to the data line and an output terminal, a color filter formed on the thin film transistor, a light blocking member formed on the thin film transistor, defining the space for storing the color filter, and including a first protection portion surrounding at least the region of the output terminal of the thin film transistor, and a pixel electrode formed on the light blocking member and the color filter and contacting the region of the output terminal surrounded by the first protection portion of the light blocking member.

Abstract: Gate lines are formed on a substrate. A gate insulating layer, an intrinsic a-Si layer, an extrinsic a-Si layer, a lower film of Cr and an upper film of Al containing metal are sequentially deposited. A photoresist having thicker first portions on wire areas and thinner second portions on channel areas is formed on the upper film. The upper film on remaining areas are wet-etched, and the lower film and the a-Si layers on the remaining areas are dry-etched along with the second portions of the photoresist. The upper film, the lower film, and the extrinsic a-Si layer on the channel areas are removed. The removal of the upper film and the lower film on the channel areas are performed by wet etching, and the first portions of the photoresist are removed after the removal of the upper film on the channel areas.

Abstract: A thin film transistor array panel including a display area having a gate line, a data line insulated from and intersecting the gate line, a thin film transistor connected to the gate line and the data line, and a pixel electrode connected to the thin film transistor, and a peripheral area formed on the circumference of the display area, according to an exemplary embodiment of the present invention, includes: a driving signal line formed with the same layer as the gate line in the peripheral area and receiving an external signal; a connection signal line formed with the same layer as the data line in the peripheral area; a disconnection prevention member overlapping the side surface of the connection signal line on the connection signal line; and a connection assistance member formed on the disconnection prevention member and connecting the driving signal line and the connection signal line.

Abstract: Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads.

Abstract: A liquid crystal display device comprises at least two insulating layers formed on a first conductive layer, a second conductive layer formed between the at least two insulating layers, a first contact hole penetrating an upper insulating layer of the at least two insulating layers on the second conductive layer, a second contact hole penetrating the at least two insulating layers and exposing a portion of the first conductive layer, and a contact part comprising a bridge electrode formed of a third conductive layer for connecting the first and second conductive layers through the first and second contact holes. The second contact hole comprises an internal hole penetrating the at least two insulating layers and an external hole surrounding the internal hole forming in the upper insulating layers.

Abstract: A liquid crystal display according to an exemplary embodiment of the present invention includes: a pixel electrode including a first subpixel electrode and a second subpixel electrode with a gap therebetween; a common electrode facing the pixel electrode; and a liquid crystal layer formed between the pixel electrode and the common electrode, and including a plurality of liquid crystal molecules, wherein the first and second subpixel electrodes include a plurality of minute branches, the first and second subpixel electrodes include a plurality of subregions having different length directions of the minute branches, and the width of the minute branches is wider than an interval between the neighboring minute branches.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A thin film array panel is provided, which includes: a plurality of signal lines including contact parts for contact with an external device; a plurality of thin film transistors connected to the signal lines; an insulating layer formed on the signal lines and the thin film transistors; and a plurality of pixel electrodes formed on the insulating layer and connected to the thin film transistors, wherein the insulating layer includes a contact portion disposed on the contact parts of the signal lines and having a thickness smaller than other portions and the contact portion of the insulating layer includes an inclined portion having an inclination angle smaller than about 45 degrees.

Abstract: A thin film transistor array panel is provided, which includes: a display cell array circuit including a plurality of gate lines, a plurality of data lines, a plurality of thin film transistors, and a plurality of pixel electrodes; a gate driving circuit supplying gate signals to the gate lines; and a signal line connected to the gate driving circuit and including first and second line segments separated from each other and a connection member connected to the first and second line segments through at least a contact hole exposing at least one of the first and the second line segments.

Abstract: A thin film transistor array panel includes: a substrate, a plurality of gate and data lines, a thin film transistor, a light blocking member, a color filter, and a pixel electrode. The substrate includes a display area having a plurality of pixels and a non-display area. The gate lines and data lines are formed on the substrate. The thin film transistor is connected to a respective gate line and data line of the plurality of gate and data lines. The light blocking member is formed on the non-display area, the gate line, the data line, and the thin film transistor. The color filter is formed on the light blocking member. The pixel electrode is formed on the color filter. The color filter covers the entire light blocking member of the non-display area.

Abstract: A display substrate includes a transistor layer, a plurality of color filters, a first blocking member, a supporting member, a circuit part, a second blocking member and a protruding member. The first blocking member is disposed between different color filters. The supporting member maintains a distance between a base substrate and a substrate facing the base substrate. A circuit part is disposed in a peripheral area surrounding a display area, and the circuit part includes a metal pattern and a contact electrode in contact with the metal pattern. The second blocking member includes substantially the same material as the first blocking member and the second blocking member covers the circuit part. The protruding member includes substantially the same material as the second blocking member, and is integrally formed with the second blocking member.

Abstract: An array substrate includes a substrate including a display area and a peripheral area surrounding the display area, a transistor layer formed in the display area of the substrate and electrically connected to a gate line and a data line, a color filter formed in a pixel region on the transistor layer, a first light blocking member disposed between adjacent color filters, a first transparent member formed on the first light blocking member to cover the first light blocking member, a first color pattern formed in a peripheral area of the substrate and including substantially the same material as the color filter, and a second transparent member including substantially the same material as the first transparent member. The second transparent member is disposed in the peripheral area of the substrate to cover the first color pattern.

Abstract: Provided are a thin-film transistor (TFT) substrate which can facilitate the formation of contact holes and has improved reliability and a method of fabricating the TFT substrate. The TFT substrate includes a gate wiring formed on an insulating substrate; a data wiring defining a pixel region by intersecting the gate wiring, the data wiring including a source electrode and a drain electrode; a plurality of black matrix barrier ribs formed along the boundaries of the pixel region; a color filter formed to cover the pixel region; a pixel electrode formed on the color filter; and a plurality of contact holes formed through the color filter near the corners of the pixel region through which the pixel electrode and the drain electrode contact each other.

Abstract: A display device according to an exemplary embodiment of the present invention includes: a plurality of pixels including switching elements; a plurality of pairs of first and second gate lines connected to the switching elements and separated from each other, transmitting a gate-on voltage for turning on the switching elements; and a plurality of data lines connected to the switching elements, transmitting data signals, wherein each pair of first and second gate lines is disposed between two adjacent pixel rows and is connected to one of the pixel rows.

Abstract: A liquid crystal display capable of reducing the stray capacitance of a non-display region and a method of manufacturing the same. The liquid crystal display includes a first substrate, gate lines and data lines intersecting each other on the first substrate to define pixels, a second substrate arranged opposite to the first substrate, a common electrode formed in a display area of the second substrate in which an image is displayed, and a floating electrode formed in a non-display region of the second substrate in which no image is displayed.

Abstract: Disclosed is a thin film transistor substrate and a system for inspecting the same. The thin film transistor substrate comprises gate wiring formed on an insulation substrate and including gate lines, and gate electrodes and gate pads connected to the gate lines; a gate insulation layer covering the gate wiring; a semiconductor layer formed over the gate insulation layer; data wiring formed over the gate insulation layer and including data pads; a protection layer covering the data wiring; auxiliary pads connected to the data pads through contact holes formed in the protection layer; and a pad auxiliary layer formed protruding a predetermined height under the data pads.

Abstract: A liquid crystal display includes a first insulating substrate including a display area and a peripheral area, a display area signal line in the display area of the first insulating substrate.

Abstract: A thin film transistor array panel including a substrate; a display area signal line; a display area thin film transistor; a peripheral area signal line; a black matrix disposed on the display area signal line, the display area thin film transistor, and the peripheral area signal line, the black matrix including a first and a second contact holes exposing the peripheral area signal line; a protrusion member disposed on the peripheral area signal line, the protrusion member overlapping the peripheral area signal line; a transparent connector disposed on the black matrix and within the peripheral area, wherein the transparent connector contacts the peripheral area signal line through at least one of the first and the second contact holes and includes a protrusion within at least one of the first and the second contact holes which corresponds to the protrusion member; and a pixel electrode.