Abstract: A data transfer circuit includes a first layer for transmitting first bits and a second layer for transmitting second bits. Each of the first layer and the second layer includes: first to mth banks configured to convert a plurality of received digital pixel signals into first to mth analog voltage signals, wherein ‘m’ denotes an integer which is greater than or equal to ‘2’; first to mth samplers configured to convert the first to mth analog voltage signals into first to mth digital transmission signals; and first to mth digital transfer units configured to respectively receive the first to mth digital transmission signals.

Abstract: An image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter having a first counter for converting an analog signal into a digital signal, and an output buffer having a first memory. A first counter test result value generated as a test result for the first counter is stored in the first memory in a test mode. The output buffer outputs the first counter test result value from the first memory to an outside of the output buffer in response to a first selection signal. The output buffer further includes a reset logic circuit for resetting the first memory depending on whether the first counter test result value is output or not. The plurality of pixels generate the analog signal in response to incident light.

Abstract: Provided are an image sensor and an image processing device including the same. The image sensor includes: a pixel array including a plurality of pixels arranged in rows and columns and configured to generate pixel signals from the plurality of pixels, a time calculator configured to receive zoom information corresponding to digital zooming, and configured to calculate a row processing time available for processing the pixel signals from the plurality of pixels included in a single row based on the zoom information, a timing generator configured to generate at least one control signal based on the row processing time; and an Analog-to-Digital Converter (ADC) configured to generate pixel data by performing sampling on the pixel signals according to the at least one control signal.

Abstract: An image sensor including a comparator configured to generate a comparison signal by comparing a ramp signal and a pixel signal with each other, a counter configured to generate a digital pixel value by counting an input clock signal according to the comparison signal, and a divider configured to control a frequency of the input clock signal according to an analog gain of the image sensor.

Abstract: An image sensor operating in a skip mode and reading out a pixel signal provided by at least one of a plurality of pixels and compensating for fixed pattern noise (FPN) in column-parallel pipelines.

Abstract: Disclosed are an image sensor having a light-emitting diode (LED) flicker mitigation function and an image processing system including the image sensor. The image processing system includes an image sensor including a plurality of pixels, the plurality of pixels configured to respectively generate pixel signals corresponding to photocharges, and configured to perform analog-to-digital conversion (ADC) on the pixel signals to generate digital pixel signals; and an image signal processor configured to process the digital pixel signals to generate image data. The image sensor operates in a first operating mode in a situation in which a light-emitting diode (LED) light is provided, and operates in a second operating mode in a general situation in which the LED light is not provided.

Abstract: In one embodiment, an image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter configured to convert analog pixel signals output from the pixels into digital signals, a first cluster configured to store a first group of digital signals among the digital signals and to output first image data, a second cluster configured to store a second group of digital signals among the digital signals and to output second image data, and at least one cluster switch connected to the first cluster and the second cluster, a first channel, and a second channel. The image sensor is configured to transmit at least one among the first image data and the second image data to at least one among the first channel and the second channel based on an operation mode.

Abstract: Provided is an image sensor including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to compare a reference voltage with an analog voltage output by the pixel array and latch and decode a comparison result. The ADC is controlled in response to clock information and a counter clock, which are obtained by expanding and encoding a master clock.

Abstract: A data transfer circuit includes a first layer for transmitting first bits and a second layer for transmitting second bits. Each of the first layer and the second layer includes: first to mth banks configured to convert a plurality of received digital pixel signals into first to mth analog voltage signals, wherein ‘m’ denotes an integer which is greater than or equal to ‘2’; first to mth samplers configured to convert the first to mth analog voltage signals into first to mth digital transmission signals; and first to mth digital transfer units configured to respectively receive the first to mth digital transmission signals.

Abstract: An integrated circuit counter includes a cascaded chain of bit counters, which are collectively configured to count a number of first edges of a counter input signal received at an input thereof and output the count as a counter output signal. The cascaded chain includes at least two bit counters, which are: (i) configured to support both counter and buffer modes of operation, and (ii) responsive to respective bypass control bit signals having values that specify whether a corresponding one of the at least two bit counters is disposed in the counter or buffer mode of operation.

Abstract: An image sensor operating in a skip mode and reading out a pixel signal provided by at least one of a plurality of pixels and compensating for fixed pattern noise (FPN) in column-parallel pipelines.

Abstract: A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data.

Abstract: A ramp signal generator includes a rising-edge current unit, a falling-edge current unit and a current-voltage converter. The rising-edge current unit provides a rising-edge output current that sequentially increases or decreases in synchronization with rising edges of a clock signal. The falling-edge current unit provides a falling-edge output current that sequentially increases or decreases in synchronization with falling edges of the clock signal. The current-voltage converter outputs a ramp voltage by converting a summed current of the rising-edge output current and the falling-edge output current.

Abstract: An image sensor including a comparator configured to generate a comparison signal by comparing a ramp signal and a pixel signal with each other, a counter configured to generate a digital pixel value by counting an input clock signal according to the comparison signal, and a divider configured to control a frequency of the input clock signal according to an analog gain of the image sensor.

Abstract: An image sensor includes a comparator configured to compare a pixel signal with a ramp signal and generate a comparison signal and a counter configured to be reset by a counter reset value based on an offset of the comparator and to generate a digital pixel signal according to the comparison signal.

Abstract: In one embodiment, an image sensor includes a pixel array including a plurality of pixels, an analog-to-digital converter configured to convert analog pixel signals output from the pixels into digital signals, a first cluster configured to store a first group of digital signals among the digital signals and to output first image data, a second cluster configured to store a second group of digital signals among the digital signals and to output second image data, and at least one cluster switch connected to the first cluster and the second cluster, a first channel, and a second channel. The image sensor is configured to transmit at least one among the first image data and the second image data to at least one among the first channel and the second channel based on an operation mode.

Abstract: A line driving circuit in which a signal characteristic is improved and a semiconductor device including the same are provided. The semiconductor device includes: a line controller arranged in a first portion of at least one line; a first driver arranged in the first portion and configured to output through the at least one line a first signal according to a control of the line controller; and a second driver arranged in a second portion of the at least one line and configured to output through the at least one line a second signal according to a level of the first signal.

Abstract: Provided is an image sensor including a pixel array including a plurality of pixels and an analog-to-digital converter (ADC) configured to compare a reference voltage with an analog voltage output by the pixel array and latch and decode a comparison result. The ADC is controlled in response to clock information and a counter clock, which are obtained by expanding and encoding a master clock.

Abstract: Image sensors include an array of image sensor pixels therein. This array of image sensor pixels includes a first focus detection pixel and at least a first color pixel. A switching network is provided, which is electrically coupled to the array. This switching network may be configured to generate a first mixed image signal by electronically mixing a focus detection signal generated by the first focus detection pixel with at least one color pixel signal generated by the at least a first color pixel. The first focus detection pixel can be a color-blind pixel, which may include a light-blocking shield mask therein.

Abstract: A digital correlated double sampling (CDS) circuit includes a first latch unit, a second latch unit and a calculating unit. The first latch unit stores digital reset component data and digital image component data by latching a count signal in response to a first control signal. The second latch unit stores the digital reset component data by latching an output of the first latch unit in response to a second control signal. The calculating unit generates digital effective image data by subtracting the digital reset component data from the digital image component data.