Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device includes a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.

Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.

Abstract: A pouch bag that can be opened and closed during the degassing process and a pouch type secondary battery comprising the same, which has an economical effect because the pouch bag surplus portion to be discarded after the degassing process does not occur. This results in a reduction of waste material in the manufacturing process.

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.

Abstract: A semiconductor memory device includes a landing pad on a substrate, a lower electrode on and connected to the landing pad, a dielectric layer on and extending along a profile of the lower electrode, an upper electrode on the dielectric layer, and an upper plate electrode on the upper electrode, the upper plate electrode including a first sub-plate electrode and a second sub-plate electrode doped with boron, a first concentration of the boron in the first sub-plate electrode being greater than a second concentration of the boron in the second sub-plate electrode.

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The semiconductor memory device comprises a semiconductor substrate that includes a cell array region and a peripheral region, a plurality of bottom electrodes on the semiconductor substrate on the cell array region, a dielectric layer that conformally covers sidewalls and top surfaces of the bottom electrodes, and a top electrode on the dielectric layer and between the bottom electrodes. The top electrode includes a first metal layer, a silicon-germanium layer, a second metal layer, and a silicon layer that are sequentially stacked. An amount of boron in the silicon-germanium layer is greater than an amount of boron in the silicon layer.

Abstract: Disclosed are semiconductor devices and their fabrication methods. The semiconductor device comprises a substrate including a peripheral block and cell blocks each including a cell center region, a cell edge region, and a cell middle region, and bit lines extending on each cell block in a first direction. The bit lines include center bit lines, middle bit lines, and edge bit lines. The bit line has first and second lateral surfaces opposite to each other in a second direction. The first lateral surface straightly extends along the first direction on the cell center region, the cell middle region, and the cell edge region. The second lateral surface straightly extends along the first direction on the cell center region and the cell edge region, and the second lateral surface extends along a third direction, that intersects the first direction and the second direction, on the cell middle region.

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Abstract: A semiconductor device may include a substrate including a cell region, a peripheral region, and a boundary region between the cell region and the peripheral region, bit lines provided on the cell region and extended in a first direction parallel to a top surface of the substrate, bit line capping patterns provided on the bit lines, and a boundary pattern provided on the boundary region. End portions of the bit lines may be in contact with a first interface of the boundary pattern, and the bit line capping patterns may include the same material as the boundary pattern.

Abstract: A semiconductor device may include a substrate including a cell region and a peripheral region, a gate stack on the peripheral region, an interlayer insulating layer on the gate stack, peripheral circuit interconnection lines on the interlayer insulating layer, and an interconnection insulating pattern between the peripheral circuit interconnection lines. The interconnection insulating pattern may include a pair of vertical portions spaced apart from each other in a first direction parallel to a top surface of the substrate and a connecting portion connecting the vertical portions to each other. Each of the vertical portions of the interconnection insulating pattern may have a first thickness at a same level as top surfaces of the peripheral circuit interconnection lines and a second thickness at a same level as bottom surfaces of the peripheral circuit interconnection lines. The first thickness may be substantially equal to the second thickness.

Abstract: Disclosed are semiconductor memory devices and their fabrication methods. The method comprises providing a substrate including a cell array region and a boundary region, forming a device isolation layer that defines active sections on an upper portion of the substrate on the cell array region, forming an intermediate layer on the substrate on the boundary region, forming on the substrate an electrode layer that covers the intermediate layer on the boundary region, forming a capping layer on the electrode layer, forming an additional capping pattern including providing a first step difference to the capping layer on the boundary region, and allowing the additional capping pattern, the capping layer, and the electrode layer to proceed an etching process to form bit lines that run across the active sections. During the etching process, the electrode layer is simultaneously exposed on the cell array region and the boundary region.

Abstract: An electrode assembly manufacturing apparatus includes a stack table, a separator supply unit, first and second electrode supply units, and a side sealing device. A stack of a first electrode, a second electrode, and a separator between the first and the second electrode are stackable on the stack table. The separator supply unit is configured for supplying the separator to the stack table. The first electrode supply unit is configured for stacking the first electrode on a section of the separator on the stack table. The second electrode supply unit stacks the second electrode on a further section of the separator on the first electrode. A side sealing device heats at least one side surface of the stack.

Abstract: An electrode assembly includes a stack and a second separator. The stack includes first and second electrodes and a first separator folded in a zigzag configuration and including spacer sections and respective side sections between the spacer sections. The first and the second electrodes are alternately disposed between first separator spacer sections The second separator extends along an upper surface, a lower surface, and at least one pair of opposing side surfaces of the stack. The side sections of the first separator define portions of the side surfaces of the stack on which the first electrode and the second electrode are not disposed. The second separator is bonded to at least one of the side sections.

Abstract: A semiconductor device includes a substrate including a cell region and a peripheral region, a cell gate electrode buried in a groove crossing a cell active portion of the cell region, a cell line pattern crossing over the cell gate electrode, the cell line pattern being connected to a first source/drain region in the cell active portion at a side of the cell gate electrode, a peripheral gate pattern crossing over a peripheral active portion of the peripheral region, a planarized interlayer insulating layer on the substrate around the peripheral gate pattern, and a capping insulating layer on the planarized interlayer insulating layer and a top surface of the peripheral gate pattern, the capping insulating layer including an insulating material having an etch selectivity with respect to the planarized interlayer insulating layer.

Abstract: The method includes forming a first dielectric layer on a substrate, forming a via in the first dielectric layer, sequentially forming a first metal pattern, a first metal oxide pattern, a second metal pattern, and an antireflective pattern on the first dielectric layer, and performing an annealing process to react the first metal oxide pattern and the second metal pattern with each other to form a second metal oxide pattern. The forming the second metal oxide pattern includes forming the second metal oxide pattern by a reaction between a metal element of the second metal pattern and an oxygen element of the first metal oxide pattern.

Abstract: The present disclosure provides a semiconductor memory device with improved element performance and reliability. The semiconductor memory device comprises a substrate, a gate electrode extending in a first direction in the substrate, a plurality of buried contacts on the substrate, and a fence in a trench between adjacent ones of the buried contacts. The fence is on the gate electrode. The fence includes a spacer film on side walls of the trench and extending in a second direction intersecting the first direction, and a filling film in the trench and on the spacer film. An upper surface of the spacer film is lower than an upper surface of the filling film with respect to the substrate.

Abstract: A semiconductor memory device comprises a substrate which includes a cell region, and a peri region defined around the cell region, the cell region including an active region defined by an element separation film, a storage pad connected to the active region of the cell region, a peri gate structure placed on the substrate of the peri region, a peri contact plug placed on both sides of the peri gate structure and connected to the substrate, a first interlayer insulating film which is placed on the storage pad and the pen contact plug, and includes a nitride-based insulating material, and an information storage unit connected to the storage pad, wherein a thickness of the first interlayer insulating film on an upper surface of the storage pad is smaller than a thickness of the first interlayer insulating film on an upper surface of the peri contact plug.

Abstract: Disclosed are a semiconductor memory device and a method of fabricating the same. The device includes a substrate including an active pattern with doped regions, a gate electrode crossing the active pattern between the doped regions, a bit line crossing the active pattern and being electrically connected to one of the doped regions, a spacer on a side surface of the bit line, a first contact coupled to another of the doped regions and spaced apart from the bit line with the spacer interposed therebetween, a landing pad on the first contact, and a data storing element on the landing pad. The another of the doped regions has a top surface, an upper side surface, and a curved top surface that extends from the top surface to the upper side surface. The first contact is in contact with the curved top surface and the upper side surface.