Abstract: The present invention relates to a de-rate matching device. The de-rate matching device in a communication system divides received data into a plurality of blocks, and simultaneously de-rate-matches data in the respective blocks.

Abstract: A liquid crystal display panel includes a first substrate, a second substrate facing the first substrate, and a liquid crystal layer interposed therebetween. The second substrate includes gate lines, data lines crossing the gate lines to define sub-pixel regions, a thin film transistor connected to a gate line and a data line, an organic passivation layer, a pixel electrode connected to the thin film transistor, a repair portion where the pixel electrode overlaps with a previous gate line, and a repair hole formed in the repair portion to penetrate the organic passivation layer. The pixel electrode is arranged in the repair hole. A method for repairing a defective pixel includes connecting a gate extending portion of the previous gate line to the pixel electrode in the repair portion using a laser, and cutting the defective pixel's drain electrode connected to the pixel electrode.

Abstract: In a display device, gate lines, which extend in a first direction, cross and are insulated from data lines, which extend in a second direction, to define pixel areas on a first base substrate. Pixels are arranged in the pixel areas, respectively, and a color filter layer including a plurality of color filter is arranged on a second base substrate that is coupled with the first base substrate. The color filters include a first sub color filter, a second sub color filter, and a third sub color filter, repeatedly arranged in the first direction and the second direction to represent different colors, respectively.

Abstract: An apparatus and method for detecting a GCL sequence using a magnitude and a sign of a real part of a I/FDFT output except an imaginary part in a wireless communication system. The apparatus includes: a modified inverse/forward discrete fourier transform (I/FDFT) processing unit for enabling that the GCL sequence class u is detected with only a real part; a real value selecting unit for selecting real parts from the output of the I/FDFT processing unit; and a maximum value detecting unit for detecting a maximum value among magnitudes of the selected real parts having a positive sign from the real value selecting unit.

Abstract: A gate drive circuit of a display device includes a plurality of stages, each stage being coupled to at least one other stage. A current stage among the stages includes a gate section, a carry section, a buffer section, and a reset section. The gate section generates a current gate signal and the carry section generates a current carry signal. The buffer section receives a previous carry signal from a previous stage, and then turns on the gate section and the carry section. The reset section receives a next carry signal from next stages, and then turns off the gate section and the carry section. As the current stage is reset in response to the next carry signal, the function of the gate drive circuit is increased.

Abstract: The present invention provides a liquid crystal display (“LCD”), a method of manufacturing the same, and a method of repairing the same capable of obtaining a wide viewing angle and improving a success ratio of repair. The LCD includes a gate line, a first data line intersecting the gate line, a thin film transistor (“TFT”) connected with the gate line and the first data line, a pixel electrode connected with the TFT, a first conductive pattern partially overlapping with a first end of the pixel electrode, a second conductive pattern partially overlapping with a second end of the pixel electrode, and a storage capacitor, wherein at least one of the first conductive pattern and the second conductive pattern partially overlaps with the first data line adjacent to the first end of the pixel electrode and a second data line adjacent to the second end of the pixel electrode, respectively.

Abstract: A thin film panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line that intersects the first signal line and includes first and second portions being substantially rectilinear and disposed on different straight lines and a connection connected to the first and the second portions; and first and second pixel electrodes disposed adjacent to the second signal line and overlapping the first and the second portions of the second signal line, respectively.

Abstract: A liquid crystal display includes a gate line (formed on an insulating substrate) including a gate electrode, a gate insulation layer formed on the gate line, a semiconductor layer formed on the gate insulation layer., and a data line and a drain electrode formed on the semiconductor layer (stripe). A borderline (side edge) of the semiconductor layer (stripe) is positioned at the outside of a borderline (side edge) of the data line. In this way, by minimizing the overlap of the data line and the pixel electrode (so that a width of the data line is smaller than that of the semiconductor layer (stripe), parasitic capacitance is reduced, so that vertical line blur can be prevented.

Abstract: The present invention relates to signal transmitting/receiving apparatuses. The signal transmitting apparatus includes an inverse discrete Fourier transform module, a cyclic prefix adding module, a preamble adding module, and a digital-analog converting module. The inverse discrete Fourier transform module receives modulated data, performs inverse discrete Fourier transform, and generates a first symbol. The cyclic prefix adding module adds a predetermined cyclic prefix to the first symbol, and generates a second symbol. The preamble adding module adds a predetermined preamble to the second symbol, and generates a third symbol. The digital-analog converting module converts the third symbol including the cyclic prefix and the preamble into an analog symbol.

Abstract: The present invention is related to a partially overlapped single-carrier crosstalk signal cancellation method and an apparatus using the same. For this purpose, the present invention provides a crosstalk canceller including a pre-processor for frequency down-shifting an input signal, a crosstalk signal cancellation module for canceling the crosstalk signal by dividing the input signal by an interpolation ratio, a post-processor for converting an output of the crosstalk signal cancellation modulation into a passband signal, and an error feedback processor for performing a decimation operation on a residual crosstalk signal and feeding backing the decimated residual crosstalk signal to the crosstalk signal cancellation module.

Abstract: The present invention relates to a method and an apparatus for cancellation of crosstalk signals using multi-dimensional coordination and vectored transmission. A method of canceling crosstalk signals in a receiver includes a step of multi-dimensionally decomposing the received signals into a user domain and a time domain, a step of calculating a transposed matrix and a diagonal matrix of a unit matrix from the received signals, a step of decoding the received signals with respect to symbols taking the user domain using the transposed matrix and the diagonal matrix of the unit matrix, and a step of decoding the signal decoded in the user domain with respect to symbols taking the time domain so as to calculate the data vectors from which the crosstalk signals are cancelled.

Abstract: A thin film panel is provided, which includes: a substrate; a first signal line formed on the substrate; a second signal line that intersects the first signal line and includes first and second portions being substantially rectilinear and disposed on different straight lines and a connection connected to the first and the second portions; and first and second pixel electrodes disposed adjacent to the second signal line and overlapping the first and the second portions of the second signal line, respectively.

Abstract: A scan driver sequentially activates scan lines of a display apparatus having m-number of scan lines. The scan driver includes a pull-up driving section and a pull-down driving section. The pull-up driving section includes a pull-up transistor that is electrically connected to an ith scan line to activate the ith scan line to be in a high level state. The pull-down driving section includes a pull-down transistor that is electrically connected to the ith scan line to inactivate the ith scan line to be in a low level state when (i+1)th scan line is activated. A gate electrode of the pull-up transistor is electrically separated from the ith scan line. The above ‘m’ is an integer greater than 1, and ‘i’ is an integer no greater than ‘m’. Therefore, display defects may be minimized, and detecting a cause of the display defect may be simplified to enhance productivity.

Abstract: A scan driver drives a display device having a plurality of gate lines transferring scan signals, and a plurality of source lines transferring data signals. The scan driver includes a shift register and a multiple signal applying unit. The shift register includes a plurality of cascade-connected stages, each stage having an output terminal electrically connected to a respective one of the plurality of gate lines. The multiple signal applying unit applies a sub scan signal and a main scan signal. The sub scan signal and the main scan signal sequentially activate each of the plurality of gate lines. Therefore, the scan lines receive the scan signal twice, so that the liquid crystal capacitors electrically connected to the gate lines receive the data voltage twice. As a result, even though the time for charging the liquid crystal capacitors may be reduced, the liquid crystal capacitors may be fully charged to enhance display quality.

Abstract: A liquid crystal display (“LCD”) includes a data interconnection line including a data line, a source electrode as a branch of the data line, and a drain electrode formed spaced apart from the source electrode, a semiconductor layer formed under the data interconnection line and connected to the source electrode and the drain electrode below the source electrode and the drain electrode and forming a channel region, and a gate interconnection line formed under the semiconductor layer and including a gate line intersecting the data line, the gate line extending in a first direction and the data line extending in a second direction, and a gate electrode branched from the gate line, wherein the gate line includes a first recess having a first width and a first length.

Abstract: An array substrate includes a display region having a plurality of pixel parts and a peripheral region surrounding the display region. The array substrate also includes a switching element, a pixel element, a metal pattern, a pixel electrode pattern and an alignment layer. The switching element is in each of the pixel parts. The switching element is electrically connected to gate and source lines. The pixel electrode is electrically connected to the switching element. The metal pattern part is in the peripheral region. The pixel electrode pattern part is on the metal pattern part. The alignment layer is on the pixel electrode and the pixel electrode pattern part. Therefore, the array substrate may be securely combined with an alignment substrate to improve an impact resistance of a display device.

Abstract: A radio network controller of an IMT-2000 asynchronous system that includes a Node-B matching radio access system for accessing to a Node-B; a traffic processing radio access system for performing a soft handover of radio traffic channels of the base transceiver stations; and an ATM switch accessible to the traffic processing radio access system, for providing a path for communicating traffic and control data in the radio network controller, switching ATM cells, providing a path for transmitting various traffic between radio network controllers and soft handover between the radio network controllers.

Abstract: The present invention relates to a thin film transistor (TFT) substrate and method of making such a TFT substrate. The structure of the TFT substrate helps prevent damage to signal lines in non-display areas.

Abstract: The present invention relates to a thin film transistor substrate including a shift register disposed at a first side of a non-display area, a gate line disposed to traverse a display area of the TFT substrate, a data line disposed to traverse the display area and cross the gate line, and a diode. The gate line has a first end and a second end. The first end is electrically coupled to the shift register. The diode is electrically coupled to the second end of the gate line and disposed at a second side of the non-display area. The diode prevents an exterior current from being introduced to the gate line at the second end.

Abstract: A system connected to a mobile station through a network and allocating a radio source to the mobile station for packet data service, the system including a base station connected to the mobile station through a wireless network, and having a physical layer connected to the mobile station through a wireless network and performing wireless access and a medium access control (MAC) layer performing service-specific resource allocation for the mobile station; and a control station having an upper layer connected to the base station through a wired network and receiving a result of service-specific resource allocation from the MAC layer, and performing as an interface between networks.