Abstract: The present disclosure provides semiconductor packages including a heat dissipation structure. In some embodiments, the semiconductor package includes a package substrate, a stacked chip disposed on the package substrate and including a lower chip and an upper chip, a memory chip disposed on the package substrate adjacent to the stacked chip, and an encapsulant encapsulating at least a portion of the stacked chip and the memory chip on the package substrate. An upper surface of the upper chip is exposed from the encapsulant. A dummy silicon chip is in contact with the upper chip on the lower chip.

Abstract: A cleaner includes: a suction motor that generates suction force; a dust separation unit that separates dust from air sucked by the suction force; a motor housing that covers the suction motor; a flow guide that surrounds an outer side of the motor housing and guides air discharged from the dust separation unit to the suction motor; and a body that forms an external appearance by surrounding the flow guide and guides air discharged from the suction motor together with the flow guide.

Abstract: A semiconductor package includes a redistribution substrate, a sub-package disposed on the redistribution substrate, a semiconductor chip disposed on the redistribution substrate, a heat dissipation structure disposed on the redistribution substrate and surrounding the sub-package and the semiconductor chip, and an encapsulant. The redistribution substrate includes a redistribution structure. The semiconductor chip is positioned side-by-side with the sub-package. The encapsulant encapsulates the sub-package, the semiconductor chip, and the heat dissipation structure.

Abstract: A semiconductor package includes a first redistribution structure, a first semiconductor device mounted on the first redistribution structure, a molding layer surrounding the first semiconductor device, a second redistribution structure disposed on the molding layer and the first semiconductor device, a plurality of vertical connection conductors vertically extending in the molding layer and electrically connecting the first redistribution pattern to the second redistribution pattern, a second semiconductor device mounted on the second redistribution structure, the second semiconductor device and the first semiconductor device vertically and partially overlapping each other, a heat dissipation pad structure contacting an upper surface of the first semiconductor device, and a heat dissipation plate disposed on the heat dissipation pad structure and spaced apart from the second semiconductor device along a first straight line extending in a horizontal direction that is parallel to the upper surface of the first

Abstract: Provided is a semiconductor package including a lower redistribution structure, an internal semiconductor chip on an upper surface of the lower redistribution structure, an upper redistribution structure electrically connected to the lower redistribution structure through a conductive post, and a molding layer between the upper redistribution structure and the lower redistribution structure, the molding layer being adjacent to the internal semiconductor chip, wherein the upper redistribution structure includes an insulating layer including a redistribution pattern and a first material configured to transmit light, and a fiducial mark formed of the first material, and a lower surface of the fiducial mark is in contact with an upper surface of the molding layer.

Abstract: An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 ?m to 1 mm. The second distance is equal to or less than 0.1 mm.

Abstract: A semiconductor package includes: a first redistribution structure including at least one first redistribution layer and at least one first insulating layer; a first semiconductor chip electrically connected to the at least one first redistribution layer and disposed on a first surface of the first redistribution structure; a second semiconductor chip disposed on an upper surface of the first semiconductor chip; a first encapsulant disposed on a second surface of the first redistribution structure opposite the first surface of the first redistribution layer; first conductive posts electrically connected to the first semiconductor chip and penetrating the first encapsulant; and under bump metallurgy (UBM) structures disposed on a lower surface of the first encapsulant, wherein at least a portion of the UBM structures overlap at least a portion of the first conductive posts in a penetration direction of the first conductive posts and are connected to the first conductive posts.

Abstract: A cleaner includes: a suction motor that generates suction force; a dust separation unit disposed under the suction motor and separates dust from air; a handle disposed behind the suction motor; and a battery disposed under the handle and behind the dust separation unit to supply power to the suction motor.

Abstract: A semiconductor package includes a redistribution structure in which at least one redistribution layer and at least one insulating layer are alternately stacked; a semiconductor chip electrically connected to the at least one redistribution layer; and bumps on the redistribution structure, wherein the redistribution structure includes vias extending from the at least one redistribution layer in a vertical stacking direction of the redistribution structure; and under bump metallurgy (UBM) structures electrically connected between the vias and the bumps and configured to face the bumps in the vertical stacking direction of the redistribution structure, wherein each of the UBM structures includes a first UBM layer including a first metal material or an alloy of the first metal material; and a second UBM layer between one of the bumps and the first UBM layer and including a second metal material.

Abstract: A packaged integrated circuit includes a redistribution layer having a plurality of electrically conductive vias extending at least partially therethrough, and a plurality of lower pads electrically connected to corresponding ones of the plurality of electrically conductive vias. A semiconductor chip is provided on the redistribution layer, and external connection terminals are provided, which electrically contact corresponding ones of the plurality of lower pads within the redistribution layer. Each of the plurality of lower pads includes: (i) a lower under-bump metallization (UBM) layer in contact with a corresponding external connection terminal, and (ii) an upper UBM layer extending on and contacting the lower UBM layer. In addition, an upper surface of the lower UBM layer has a greater lateral width dimension relative to an upper surface of the upper UBM layer, which contacts a corresponding electrically conductive via.

Abstract: A cleaner includes: a main body that has an opening; a suction motor that is disposed in the main body and generates suction force; and a filter unit that includes an exhaust filter for filtering air discharged from the suction motor, the filter unit being inserted into the main body through the opening and being separated from the main body, wherein when the filter unit is combined with the main body, a portion of the filter unit protrudes out of the main body, and a portion of the exhaust filter is positioned inside the main body and the other portion of the exhaust filter is positioned outside the main body.

Abstract: A semiconductor package includes a memory chip having chip pads on a first surface thereof. A redistribution layer is formed on the first surface of the memory chip. The redistribution layer is electrically connected to the chip pads. The redistribution layer has first redistribution pads on a first surface of the redistribution layer in a first region and a plurality of second redistribution pads on the first surface of the redistribution layer in a second region thereof. A processor chip is disposed on the first region of the redistribution layer and is electrically connected to the first redistribution pads. A sealing member is disposed on the first surface of the redistribution layer and covers the processor chip. Conductive structures are on the second region and penetrate through the sealing member and extend upwardly in a vertical direction away from the second redistribution pads.

Abstract: A semiconductor package includes a redistribution wiring layer having a first surface and a second surface opposite to the first surface, a conductive bump on the first surface, and a first semiconductor device on the conductive bump. The redistribution wiring layer includes redistribution wirings having an uppermost redistribution wiring, a bonding pad, and an uppermost insulating layer. The uppermost redistribution wiring has a redistribution via and a redistribution line on the redistribution via. The bonding pad disposes on the redistribution line of the uppermost redistribution wiring, and the conductive bump is disposed on the bonding pad. The uppermost insulating layer overlapping (e.g., covering) the uppermost redistribution wiring and having an opening exposing a portion of the bonding pad.

Abstract: A semiconductor package includes a first redistribution substrate, a semiconductor chip provided on a top surface of the first redistribution substrate, a conductive structure provided on the top surface of the first redistribution substrate and spaced apart from the semiconductor chip, a molding layer provided on the first redistribution substrate and covering a side surface of the semiconductor chip and a side surface of the conductive structure, and a second redistribution substrate on the molding layer and the conductive structure. The conductive structure includes a first conductive structure provided on the first redistribution substrate, and a second conductive structure provided on a top surface of the first conductive structure. The second redistribution substrate includes an insulating layer. At least a portion of a top surface of the second conductive structure directly contacts the insulating layer of the second redistribution substrate.

Abstract: A cleaner includes: a main body that has an opening; a suction motor that is disposed in the main body and generates suction force; and a filter unit that includes an exhaust filter for filtering air discharged from the suction motor, the filter unit being inserted into the main body through the opening and being separated from the main body, wherein when the filter unit is combined with the main body, a portion of the filter unit protrudes out of the main body, and a portion of the exhaust filter is positioned inside the main body and the other portion of the exhaust filter is positioned outside the main body.

Abstract: A cleaner includes: a suction motor that generates suction force; a dust separation unit that separates dust from air sucked by the suction force; a motor housing that covers the suction motor; a flow guide that surrounds an outer side of the motor housing and guides air discharged from the dust separation unit to the suction motor; and a body that forms an external appearance by surrounding the flow guide and guides air discharged from the suction motor together with the flow guide.

Abstract: Disclosed are packages and their fabrication methods. The package includes: a lower substrate with an upper pad; a lower chip on the lower substrate; a mold layer on the lower chip and the lower substrate; a post extending through the mold layer and provided on the upper pad around the lower chip, the post having a diameter less than a diameter of the upper pad; and an upper substrate on the post and the mold layer, the upper substrate including a lower pad having a diameter greater than the diameter of the post.

Abstract: A user terminal device includes a display; at least one sensor; a communication module; and a processor operatively connected to the display, the at least one sensor, and the communication module, wherein the processor is configured to, based on receiving a user utterance voice, determine whether or not a response screen corresponding to the user utterance voice is able to be provided through the display on the basis of at least one of a sensed value obtained from the at least one sensor or an inactive period of the display, based on determining that the response screen is unable to be provided through the display, receive current status information of at least one external device connected to the user terminal device through the communication module, determine one external device among the at least one external device to display the response screen on the basis of the current status information of the at least one external device, obtain the response screen to the user utterance voice, and transmit the respo