Patents by Inventor HYEONJEONG HWANG

HYEONJEONG HWANG has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220375829
    Abstract: Disclosed is a semiconductor package comprising a first redistribution substrate; a solder ball on a bottom surface of the first redistribution substrate; a second redistribution substrate; a semiconductor chip between a top surface of the first redistribution substrate and a bottom surface of the second redistribution substrate; a conductive structure electrically connecting the first redistribution substrate and the second redistribution substrate, the conductive structure laterally spaced apart from the semiconductor chip and including a first conductive structure and a second conductive structure in direct contact with a top surface of the first conductive structure; and a conductive seed pattern between the first redistribution substrate and the first conductive structure. A material of first conductive structure and a material of the second conductive structure may be different from a material of the solder ball.
    Type: Application
    Filed: November 23, 2021
    Publication date: November 24, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hyeonjeong Hwang, Minjung Kim, Dongkyu Kim, Taewon Yoo
  • Publication number: 20220367403
    Abstract: A semiconductor package includes a redistribution substrate including a conductive structure having a lower conductive pattern and a redistribution structure electrically connected to the lower conductive pattern, on the lower conductive pattern, an insulating structure covering at least a side surface of the redistribution structure, and a protective layer between the lower conductive pattern and the insulating structure, a semiconductor chip on the redistribution substrate, and a lower connection pattern below the redistribution substrate and electrically connected to the lower conductive pattern. The protective layer includes a first portion in contact with at least a portion of an upper surface of the lower conductive pattern, and a second portion in contact with at least a portion of a side surface of the lower conductive pattern.
    Type: Application
    Filed: April 1, 2022
    Publication date: November 17, 2022
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Seokhyun LEE, Dongkyu KIM, Kyounglim SUK, Hyeonjeong HWANG
  • Publication number: 20220328389
    Abstract: A semiconductor package comprises a first redistribution substrate including first interconnection layers sequentially stacked on each other, a semiconductor chip mounted on the first redistribution substrate, a mold layer disposed on the first redistribution substrate and surrounding the semiconductor chip, a second redistribution substrate disposed on the mold layer and including second interconnection layers sequentially stacked on each other, a connection terminal disposed beside the semiconductor chip to connect the first and second redistribution substrates to each other, and outer terminals disposed on a bottom surface of the first redistribution substrate. Each of the first and second interconnection layers may include an insulating layer and a wire pattern in the insulating layer. The first redistribution substrate may have substantially the same thickness as the second redistribution substrate, and the first interconnection layers may be thinner than the second interconnection layers.
    Type: Application
    Filed: November 24, 2021
    Publication date: October 13, 2022
    Inventors: HYEONJEONG HWANG, KYOUNG LIM SUK, SEOKHYUN LEE, JAEGWON JANG
  • Publication number: 20220328388
    Abstract: A semiconductor package includes a semiconductor chip, a lower redistribution layer disposed under the semiconductor chip, the lower redistribution layer including a plurality of lower insulating layers, a plurality of lower redistribution patterns, and a plurality of lower conductive vias, a lower passivation layer disposed under the lower redistribution layer and provided with a recess at a bottom surface of the lower passivation layer, an under bump metallization (UBM) pad disposed in the first recess, a UBM protective layer disposed in the first recess and connected to the lower conductive vias while covering a top surface and opposite side surfaces of the UBM pad, and an outer connecting terminal connected to a bottom surface of the UBM pad. The bottom surface of the UBM pad is positioned at a first depth from the bottom surface of the lower passivation layer.
    Type: Application
    Filed: October 22, 2021
    Publication date: October 13, 2022
    Inventors: Hyeonjeong HWANG, Kyounglim SUK, Seokhyun LEE
  • Publication number: 20220165778
    Abstract: An image sensor package includes a glass substrate configured to focus incident light, a first redistribution layer and a second redistribution layer both disposed under the glass substrate while being horizontally spaced apart from each other by a first distance, an image sensor disposed such that an upper surface thereof is vertically spaced apart from both a lower surface of the first redistribution layer and a lower surface of the second redistribution layer by a second distance, and a first connector that connects both the first redistribution layer and the second redistribution layer to the image sensor. The thickness of the glass substrate is 0.6 to 0.8 mm. The first distance is smaller than the horizontal length of the image sensor by 50 ?m to 1 mm. The second distance is equal to or less than 0.1 mm.
    Type: Application
    Filed: June 30, 2021
    Publication date: May 26, 2022
    Inventors: Minjung Kim, Dongkyu Kim, Kyounglim Suk, Jaegwon Jang, Hyeonjeong Hwang
  • Publication number: 20220037294
    Abstract: A semiconductor package includes a first redistribution substrate, a first semiconductor chip mounted on the first redistribution substrate, a first molding layer on the first redistribution substrate and covering a top surface and lateral surfaces of the first semiconductor chip, a second redistribution substrate on the first molding layer, and an adhesive film between the second redistribution substrate and the first molding layer. The adhesive film is spaced apart from the first semiconductor chip and covers a top surface of the first molding layer. A lateral surface of the adhesive film is coplanar with a lateral surface of the second redistribution substrate.
    Type: Application
    Filed: February 25, 2021
    Publication date: February 3, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: HYEONJEONG HWANG, KYOUNG LIM SUK, SEOKHYUN LEE, JAEGWON JANG