Patents by Inventor Hyeoung-Won Seo

Hyeoung-Won Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11088144
    Abstract: A semiconductor device includes a substrate comprising a plurality of active regions extending in a first direction and a device isolation region electrically isolating the plurality of active regions, a gate trench extending across the plurality of active regions and the device isolation region, a gate structure extending in the gate trench of each of and along opposite sidewalls of the plurality of active regions, a gate dielectric film formed between the gate trench and the gate structure in each of the plurality of active regions, and an insulating barrier film provided in each of the plurality of active regions under the gate trench spaced apart from a lower surface of the gate trench and extending in an extension direction of the gate trench.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: August 10, 2021
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeoung-won Seo
  • Publication number: 20200161306
    Abstract: A semiconductor device includes a substrate comprising a plurality of active regions extending in a first direction and a device isolation region electrically isolating the plurality of active regions, a gate trench extending across the plurality of active regions and the device isolation region, a gate structure extending in the gate trench of each of and along opposite sidewalls of the plurality of active regions, a gate dielectric film formed between the gate trench and the gate structure in each of the plurality of active regions, and an insulating barrier film provided in each of the plurality of active regions under the gate trench spaced apart from a lower surface of the gate trench and extending in an extension direction of the gate trench.
    Type: Application
    Filed: August 1, 2019
    Publication date: May 21, 2020
    Inventor: Hyeoung-won Seo
  • Patent number: 9224619
    Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.
    Type: Grant
    Filed: September 30, 2014
    Date of Patent: December 29, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seol-Min Yi, Dae-Hyun Moon, Joon-Seok Moon, Se-Keun Park, Hyeoung-Won Seo
  • Publication number: 20150221742
    Abstract: The semiconductor device includes a substrate, a trench formed in the substrate, a gate insulation layer conformally formed on the inner surface of the trench, buried gate electrodes formed on the gate insulation layer and filling a portion of the trench, and a capping layer formed on the buried gate electrodes and filling the trench. The buried gate electrode include a first gate electrode and a second gate electrode surrounding a bottom portion of the first gate electrode, and an air gap is provided between a top portion of the first gate electrode and the gate insulation layer.
    Type: Application
    Filed: September 30, 2014
    Publication date: August 6, 2015
    Inventors: Seol-Min YI, Dae-Hyun MOON, Joon-Seok MOON, Se-Keun PARK, Hyeoung-Won SEO
  • Patent number: 8895400
    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
    Type: Grant
    Filed: May 17, 2012
    Date of Patent: November 25, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Yun-Gi Kim, Young-Woong Son, Bong-Soo Kim
  • Patent number: 8873277
    Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Grant
    Filed: October 10, 2012
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
  • Patent number: 8871614
    Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.
    Type: Grant
    Filed: December 7, 2010
    Date of Patent: October 28, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-joon Kim, Hyeoung-won Seo
  • Patent number: 8482045
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: July 16, 2012
    Date of Patent: July 9, 2013
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8310859
    Abstract: A semiconductor memory device includes a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Grant
    Filed: September 30, 2009
    Date of Patent: November 13, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Soo-ho Shin, Won-woo Lee, Jeong-soo Park, Young-yong Byun, Seong-jin Jang, Sang-woong Shin
  • Publication number: 20120273898
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.
    Type: Application
    Filed: July 16, 2012
    Publication date: November 1, 2012
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20120264280
    Abstract: A semiconductor device includes a semiconductor substrate having a cell region and a peripheral circuit region defined therein. A buried word line is disposed in the substrate in the cell region and has a top surface lower than top surfaces of cell active regions in the cell region. A gate line is disposed on the substrate in the peripheral circuit region. A word line interconnect is disposed in the substrate in the peripheral circuit region, the word line interconnect including a first portion contacting the buried word line and having a top surface lower than a top surfaces of the cell active regions and a second portion that is overlapped by and in contact with the gate line.
    Type: Application
    Filed: May 17, 2012
    Publication date: October 18, 2012
    Inventors: Hyeoung-Won Seo, Yun-Gi Kim, Young-Woong Son, Bong-Soo Kim
  • Patent number: 8283714
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: April 13, 2011
    Date of Patent: October 9, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Patent number: 8174065
    Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.
    Type: Grant
    Filed: July 21, 2010
    Date of Patent: May 8, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo
  • Patent number: 8164119
    Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
    Type: Grant
    Filed: January 27, 2011
    Date of Patent: April 24, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Byung-Hyug Roh, Seong-Goo Kim, Sang-Min Jeon
  • Patent number: 8053307
    Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Bong-Soo Kim
  • Patent number: 8039896
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Patent number: 8022457
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20110186923
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.
    Type: Application
    Filed: April 13, 2011
    Publication date: August 4, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20110147800
    Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
    Type: Application
    Filed: January 27, 2011
    Publication date: June 23, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-Won SEO, Byung-Hyug ROH, Seong-Goo Kim, Sang-Min Jeon
  • Patent number: 7952129
    Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Dong-gun Park, Seong-goo Kim