Patents by Inventor Hyeoung-Won Seo

Hyeoung-Won Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8053307
    Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
    Type: Grant
    Filed: April 14, 2010
    Date of Patent: November 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Bong-Soo Kim
  • Patent number: 8039896
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Grant
    Filed: May 9, 2008
    Date of Patent: October 18, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Patent number: 8022457
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device. Thus, effective space arrangement of a memory cell is possible such that a 4F2 structure is constituted, and a conventional line and contact forming process can be applied such that highly integrated semiconductor memory device is readily fabricated.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 20, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20110186923
    Abstract: Channels of two transistors are vertically formed on portions of two opposite side surfaces of one active region, and gate electrodes are vertically formed on a device isolation layer contacting the channels of the active region. A common bit line contact plug is formed in the central portions of the active region, two storage node contact plugs are formed on both sides of the bit line contact plug, and an insulating spacer is formed on a side surface of the bit line contact plug. A word line, a bit line, and a capacitor are sequentially stacked on the semiconductor substrate, like a conventional semiconductor memory device.
    Type: Application
    Filed: April 13, 2011
    Publication date: August 4, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won Seo, Bong-soo Kim, Dong-gun Park, Kang-yoon Lee, Jae-man Yoon, Seong-goo Kim, Seung-bae Park
  • Publication number: 20110147800
    Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
    Type: Application
    Filed: January 27, 2011
    Publication date: June 23, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-Won SEO, Byung-Hyug ROH, Seong-Goo Kim, Sang-Min Jeon
  • Patent number: 7952129
    Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.
    Type: Grant
    Filed: June 11, 2010
    Date of Patent: May 31, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Dong-gun Park, Seong-goo Kim
  • Publication number: 20110076856
    Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.
    Type: Application
    Filed: December 7, 2010
    Publication date: March 31, 2011
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Sun-joon KIM, Hyeoung-won SEO
  • Patent number: 7888720
    Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
    Type: Grant
    Filed: October 2, 2007
    Date of Patent: February 15, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Byung-Hyug Roh, Seong-Goo Kim, Sang-Min Jeon
  • Patent number: 7867825
    Abstract: A semiconductor die and a related method of processing a semiconductor wafer are disclosed in which a first interlayer insulator having a recess region of varying configuration and defining a scribe line is associated with at least one protective layer formed with a characterizing inclined side surface.
    Type: Grant
    Filed: August 29, 2007
    Date of Patent: January 11, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sun-joon Kim, Hyeoung-won Seo
  • Publication number: 20100285654
    Abstract: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.
    Type: Application
    Filed: July 20, 2010
    Publication date: November 11, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyeoung-won Seo
  • Publication number: 20100283094
    Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.
    Type: Application
    Filed: July 21, 2010
    Publication date: November 11, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo
  • Publication number: 20100267210
    Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 21, 2010
    Inventors: Hyeoung-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Bong-Soo Kim
  • Publication number: 20100244124
    Abstract: Embodiments according to the inventive concept can provide semiconductor devices including a substrate and a plurality of active pillars arranged in a matrix on the substrate. Each of the pillars includes a channel part that includes a channel dopant region disposed in a surface of the channel part. A gate electrode surrounds an outer surface of the channel part. The plurality of active pillars may be arranged in rows in a first direction and columns in a second direction crossing the first direction.
    Type: Application
    Filed: June 11, 2010
    Publication date: September 30, 2010
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Dong-gun Park, Seong-goo Kim
  • Patent number: 7781285
    Abstract: There are provided a semiconductor device having a vertical transistor and a method of fabricating the same. The method includes preparing a semiconductor substrate having a cell region and a peripheral circuit region. Island-shaped vertical gate structures two-dimensionally aligned along a row direction and a column direction are formed on the substrate of the cell region. Each of the vertical gate structures includes a semiconductor pillar and a gate electrode surrounding a center portion of the semiconductor pillar. A bit line separation trench is formed inside the semiconductor substrate below a gap region between the vertical gate structures, and a peripheral circuit trench confining a peripheral circuit active region is formed inside the semiconductor substrate of the peripheral circuit region. The bit line separation trench is formed in parallel with the column direction of the vertical gate structures.
    Type: Grant
    Filed: June 9, 2006
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-Soo Kim, Kang-Yoon Lee, Dong-Gun Park, Jae-Man Yoon, Seong-Goo Kim, Hyeoung-Won Seo
  • Patent number: 7781851
    Abstract: A semiconductor device and a method of manufacturing the same reduce die-warpage. The semiconductor device includes a substrate and a first layer of material extending substantially over the entire surface of the substrate. A stress-relieving pattern exists in and traverses the first layer so as to partition the first layer into at least two discrete sections. The stress-relieving pattern may be in the form of an interface between the discrete sections of the first layer, or a wall of material different from the material of the first layer.
    Type: Grant
    Filed: December 30, 2005
    Date of Patent: August 24, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Hyeoung-won Seo
  • Patent number: 7776692
    Abstract: A semiconductor device having a vertical channel capable of reducing the interface contact resistance between a gate electrode surrounding an active pillar and a word line connecting the gate electrode and a method of manufacturing the same is provided. The semiconductor device includes a plurality of active pillars extending in a direction perpendicular to a surface of a semiconductor substrate. A word line structure is formed on an outer periphery for connecting the active pillars disposed in the same row or column. Top and bottom source/drain regions are formed over and under the active pillars, respectively, in relation to the word line structure.
    Type: Grant
    Filed: February 6, 2007
    Date of Patent: August 17, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-man Yoon, Bong-soo Kim, Hyeoung-won Seo, Kang-yoon Lee
  • Patent number: 7759198
    Abstract: Methods of manufacturing a semiconductor device include forming a matrix of active pillars including a channel part on a substrate. Channel dopant regions are formed in the channel parts of the active pillars. Gate electrodes are formed on an outer surface of the channel parts that surround the channel dopant regions. The matrix of active pillars may be arranged in rows in a first direction and in columns in a second direction crossing the first direction on the substrate.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: July 20, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Dong-gun Park, Seong-goo Kim
  • Patent number: 7749846
    Abstract: A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device.
    Type: Grant
    Filed: March 13, 2008
    Date of Patent: July 6, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Sun-Hoo Park, Soo-Ho Shin
  • Patent number: 7728373
    Abstract: A semiconductor device may include a substrate having a cell active region. A cell gate electrode may be formed in the cell active region. A cell gate capping layer may be formed on the cell gate electrode. At least two cell epitaxial layers may be formed on the cell active region. One of the at least two cell epitaxial layers may extend to one end of the cell gate capping layer and another one of the at least two cell epitaxial layers may extend to an opposite end of the cell gate capping layer. Cell impurity regions may be disposed in the cell active region. The cell impurity regions may correspond to a respective one of the at least two cell epitaxial layers.
    Type: Grant
    Filed: February 12, 2007
    Date of Patent: June 1, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Jae-Man Yoon, Kang-Yoon Lee, Bong-Soo Kim
  • Patent number: 7696570
    Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: April 13, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Du-Heon Song, Sang-Hyun Lee