Patents by Inventor Hyeoung-Won Seo

Hyeoung-Won Seo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100080044
    Abstract: According to some of the inventive concepts, a semiconductor memory device may include a plurality of memory cell blocks including a first memory cell block having bit lines, an edge sense amplifier block including edge sense amplifiers coupled to a portion of the bit lines of the first memory cell block, and a balancing capacitor unit coupled to the edge sense amplifiers.
    Type: Application
    Filed: September 30, 2009
    Publication date: April 1, 2010
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won SEO, Young-yong BYUN, Seong-jin JANG, Sang-woong SHIN, Soo-ho SHIN, Won-woo LEE, Jeong-soo PARK
  • Patent number: 7659597
    Abstract: An integrated circuit device includes a substrate including a trench therein and a conductive plug wire pattern in the trench. The conductive plug wire pattern includes a recessed portion that exposes portions of opposing sidewalls of the trench, and an integral plug portion that protrudes from a surface of the recessed portion to provide an electrical connection to at least one other conductive wire pattern on a different level of metallization. A surface of the plug portion may protrude to a substantially same level as a surface of the substrate adjacent to and outside the trench, and the surface of the recessed portion may be below the surface of the substrate outside the trench. Related fabrication methods are also discussed.
    Type: Grant
    Filed: February 16, 2007
    Date of Patent: February 9, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seong-Goo Kim, Yun-Gi Kim, Jae-Man Yoon, Hyeoung-Won Seo
  • Patent number: 7619281
    Abstract: A semiconductor device having a buried gate line with a shaped gate trench and a method of fabricating the same are disclosed. The semiconductor device includes a trench isolation layer provided in a semiconductor substrate to define a multi-surfaced active region/channel. A gate line extending to the trench isolation layer fills a portion of the gate trench. The gate trench is formed with a series of depressions to accommodate peaks in the channel. The combination of depressions/peaks operate to increase the effective area of the channel, thereby enabling smaller channel semiconductor devices to be formed without increasing the width thereof.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: November 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Young-Woong Son, Kang-Yoon Lee, Bong-Soo Kim
  • Patent number: 7586149
    Abstract: A circuit device including vertical transistors connected to buried bitlines and a method of manufacturing the circuit device. The circuit device includes a semiconductor substrate including a peripheral circuit region and left and right cell regions at both sides of the peripheral circuit region, bottom active regions arranged on the semiconductor substrate to be spaced apart from one another in a column direction and to extend from the peripheral circuit region alternately to the left cell region and the right cell region in a row direction, channel pillars protruding from the bottom active regions in a vertical direction and arranged to be aligned in the row direction and spaced apart from one another, gate electrodes provided with a gate dielectric layer and attached to surround side surfaces of the channel pillars, and buried bitlines extending along the bottom active regions, the bottom active regions including a bottom source/drain region.
    Type: Grant
    Filed: October 2, 2006
    Date of Patent: September 8, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jae-man Yoon, Dong-gun Park, Kang-yoon Lee, Choong-ho Lee, Bong-soo Kim, Seong-goo Kim, Hyeoung-won Seo, Seung-bae Park
  • Patent number: 7557410
    Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: July 7, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Woo Lee, Cheol-Ju Yun, Hyeoung-Won Seo
  • Patent number: 7534708
    Abstract: For fabricating a field effect transistor, an extra-doped channel region is formed below a surface of a semiconductor substrate. An opening is formed in the semiconductor substrate into the extra-doped channel region. A gate insulator is formed at walls of the opening such that the extra-doped channel region abuts the gate insulator at a bottom portion of the opening. The opening is filled with a gate electrode. Such an extra-doped channel region prevents undesired body effect in the field effect transistor.
    Type: Grant
    Filed: June 14, 2006
    Date of Patent: May 19, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-Hyun Kim, Du-Heon Song, Sang-Hyun Lee, Hyeoung-Won Seo, Dae-Joong Won
  • Publication number: 20090114999
    Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
    Type: Application
    Filed: January 8, 2009
    Publication date: May 7, 2009
    Applicant: Samsung Electroncs Co., Ltd.
    Inventors: Hyeoung-Won SEO, Du-Heon SONG, Sang-Hyun LEE
  • Patent number: 7524733
    Abstract: According to some embodiments of the invention, a method includes preparing a semiconductor substrate having an active region, doping channel ions in the active region, forming a planarized selective epitaxial growth (SEG) layer in a predetermined region of the active region doped with the channel ions, sequentially forming a gate insulating layer, a gate conductive layer and a gate hard mask layer on the semiconductor substrate having the planarized SEG layer, forming a gate pattern crossing the active region by sequentially patterning the gate hard mask layer and the gate conductive layer, the planarized SEG layer being located at one side of the gate pattern, and forming source/drain regions by implanting impurity ions using the gate pattern as an ion implantation mask. Accordingly, there is provided an asymmetric source/drain transistor capable of preventing a leakage current by diffusing the channel ions into the SEG layer.
    Type: Grant
    Filed: April 16, 2007
    Date of Patent: April 28, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Nak-Jin Son, Du-Heon Song, Jun Seo
  • Patent number: 7491603
    Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a channel region in a channel-portion hole. Methods include forming embodiments of the transistor having a channel-portion hole disposed in a semiconductor substrate. A channel-portion trench pad and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line insulating layer pattern and a word line pattern are sequentially stacked on the channel-portion layer and fill the channel-portion hole, disposed on the semiconductor substrate. The channel-portion layer is formed to contact the semiconductor substrate through a portion of sidewall of the channel-portion hole, and forms a channel region under the word line pattern. Punchthrough is prevented between electrode impurity regions corresponding to source and drain regions.
    Type: Grant
    Filed: March 4, 2005
    Date of Patent: February 17, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Du-Heon Song, Sang-Hyun Lee
  • Patent number: 7482222
    Abstract: A semiconductor device comprises a plurality of gate structures formed on a substrate, a gate spacer formed on a sidewall of the gate structures, a semiconductor pattern formed on the substrate between the gate structures, a first impurity region and a second impurity region formed in the semiconductor pattern and at surface portions of the substrate, respectively, wherein the first and second impurity regions include a first conductive type impurity, and a channel doping region surrounding the first impurity region, wherein the channel doping region includes a second conductive type impurity.
    Type: Grant
    Filed: June 27, 2007
    Date of Patent: January 27, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jin-Woo Lee, Cheol-Ju Yun, Hyeoung-Won Seo
  • Publication number: 20080254608
    Abstract: A method of forming a contact structure includes forming an isolation region defining active regions in a semiconductor substrate. Gate patterns extending to the isolation region while crossing the active regions are formed. A sacrificial layer is formed on the semiconductor substrate having the gate patterns. Sacrificial patterns remaining on the active regions are formed by patterning the sacrificial layer. Molding patterns are formed on the isolation region. Contact holes exposing the active regions at both sides of the gate patterns are formed by etching the sacrificial patterns using the molding patterns and the gate patterns as an etching mask. Contact patterns respectively filling the contact holes are formed. The disclosed method of forming a contact structure may be used in fabricating a semiconductor device.
    Type: Application
    Filed: March 13, 2008
    Publication date: October 16, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-Won SEO, Sun-Hoo PARK, Soo-Ho SHIN
  • Patent number: 7429505
    Abstract: Methods of fabricating a fin field effect transistor (FinFET) are disclosed. Embodiments of the invention provide methods of fabricating FinFETs by optimizing a method for forming the fin so that a short channel effect is prevented and high integration is achieved. Accordingly, the fin which has a difficulty in its formation using the current photolithography-etching technique may be readily formed.
    Type: Grant
    Filed: November 16, 2006
    Date of Patent: September 30, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Woun-Suck Yang, Du-Heon Song, Jae-Man Yoon
  • Publication number: 20080211013
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Application
    Filed: May 9, 2008
    Publication date: September 4, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Publication number: 20080203587
    Abstract: A semiconductor device comprises a semiconductor substrate including a first core region and a second core region between which a cell array region is interposed, a first conductive line and a second conductive line extending to the first core region across the cell array region, and a third conductive line and a fourth conductive line extending to the second core region across the cell array region, wherein a line width of the first through fourth conductive lines is smaller than a resolution limit in a lithography process.
    Type: Application
    Filed: October 2, 2007
    Publication date: August 28, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-Won Seo, Byung-Hyug Roh, Seong-Goo Kim, Sang-Min Jeon
  • Publication number: 20080179647
    Abstract: A semiconductor device comprising a barrier insulating layer and a related method of fabrication is disclosed. The semiconductor device semiconductor substrate includes a plurality of active regions, wherein active regions are defined by a device isolation layer and are disposed along a first direction; a plurality of bit line electrodes connected to the active regions, wherein each of the bit line electrodes extends along a second direction; and a plurality of first barrier insulating layers. Each of the first barrier insulating layers extends along a third direction, at least one of the first barrier insulating layers is disposed on a corresponding first portion of the device isolation layer disposed between two of the active regions, the two of the active regions are adjacent along the first direction, and the first direction and the second direction differ from one another.
    Type: Application
    Filed: December 26, 2007
    Publication date: July 31, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyeoung-won Seo, Dong-hyun Kim, Kang-yoon Lee, Seong-goo Kim
  • Patent number: 7393769
    Abstract: According to some embodiments of the invention, transistors of a semiconductor device have a punchthrough protection layer, and methods of forming the same are provided. A channel-portion hole extends downward from a main surface of a semiconductor substrate. A punchthrough protection layer and a channel-portion layer are sequentially formed at a lower portion of the channel-portion hole. A word line pattern fills an upper portion of the channel-portion hole, and is formed on the semiconductor substrate. The word line pattern is formed to have a word line and a word line capping layer pattern stacked thereon, and the channel-portion layer is a channel region. The punchthrough protection layer can reduce a leakage current of a capacitor of the transistor embodied in a DRAM.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: July 1, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Ki-Nam Kim, Woun-Suck Yang, Du-Heon Song
  • Patent number: 7387931
    Abstract: In a semiconductor memory device having a vertical channel transistor a body of which is connected to a substrate and a method of fabricating the same, the semiconductor memory device includes a semiconductor substrate including a plurality of pillars arranged spaced apart from one another, and each of the pillars includes a body portion and a pair of pillar portions extending from the body portion and spaced apart from each other. A gate electrode is formed to surround each of the pillar portions. A bitline is disposed on the body portion to penetrate a region between a pair of the pillar portions of each of the first pillars arranged to extend in a first direction. A wordline is disposed over the bitline, arranged to extend in a second direction intersecting the first direction, and configured to contact the side surface of the gate electrode. A first doped region is formed in the upper surface of each of the pillar portions of the pillar.
    Type: Grant
    Filed: October 11, 2006
    Date of Patent: June 17, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-won Seo, Jae-man Yoon, Kang-yoon Lee, Dong-gun Park, Bong-soo Kim, Seong-goo Kim
  • Patent number: 7378320
    Abstract: A MOS (metal oxide semiconductor) transistor with a trench-type gate is fabricated with a channel stopping region for forming an asymmetric channel region for reducing short channel effects. For example in fabricating an N-channel MOS transistor, a gate structure is formed within a trench that is within a P-well. A channel stopping region with a P-type dopant is formed to a first side of the trench to completely contain an N-type source junction therein. An N-type drain junction is formed within a LDD region to a second side of the trench, thus forming the asymmetric channel region.
    Type: Grant
    Filed: December 23, 2004
    Date of Patent: May 27, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Dong-Hyun Kim, Du-Heon Song, Sang-Hyun Lee
  • Patent number: 7368352
    Abstract: In a semiconductor device and a method of fabricating the same, a vertical channel transistor has a cell occupation area of 4F2.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: May 6, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bong-soo Kim, Jae-man Yoon, Seong-goo Kim, Hyeoung-won Seo, Dong-gun Park, Kang-yoon Lee
  • Patent number: 7354827
    Abstract: According to embodiments of the invention, a transistor includes a semiconductor substrate having an active region. A channel trench is disposed to cross the active region. A gate insulating layer covers an inner wall of the channel trench. A gate pattern is disposed to fill the channel trench and to extend over a main surface of the semiconductor substrate. Source/drain regions having a first conductivity are disposed in the active region at both sides of the channel trench. A channel impurity region having a second conductivity is disposed beneath one of the source/drain regions to be in contact with at least a sidewall of the channel trench.
    Type: Grant
    Filed: April 6, 2005
    Date of Patent: April 8, 2008
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyeoung-Won Seo, Du-Heon Song, Sun-Joon Kim, Jin-Woo Lee