Abstract: A method of fabricating a flash memory having a U-shape floating gate is provided. The method includes forming adjacent isolation layers separated by a gap and forming a tunnel oxide layer in the gap. After a conductive layer is formed on the tunnel oxide layer to a thickness not to fill the gap, a polishing sacrificial layer is formed on the conductive layer. The sacrificial layer and the conductive layer on the isolation layers are removed, thereby forming a U-shape floating gate self-aligned in the gap, and concurrently forming a sacrificial layer pattern within an inner portion of the floating gate. Selected isolation layers are then recessed to expose sidewalls of the floating gate. The sacrificial layer pattern is then removed from the floating gate to expose an upper surface of the floating gate.

Abstract: A cleaning solution includes acetic acid, an inorganic acid, a fluoride compound, and deionized water, and may further include a corrosion inhibitor, a chelating agent, or a combination thereof. The cleaning solution may be used in the formation of a metal pattern in which a metal film including ruthenium is formed on a surface of a substrate, and a portion of the metal film is dry-etched to form a metal film pattern. After dry-etching, the metal film pattern is cleaned with the cleaning solution to remove an etching by-product layer around the metal film pattern. The cleaning solution may also be used to remove an etching by-product layer around an oxide film pattern prior to dry-etching of the metal film.

Abstract: Etching solutions are disclosed for etching low-k dielectric layers on substrates, said solutions including effective proportions of an oxidant for oxidizing a low-k dielectric layer and effective proportions of an oxide etchant for removing oxides. It is possible to easily remove a low-k dielectric layer using such etching solutions by a single-stage treatment process.

Abstract: A wet-etch composition may include: peracetic acid (PAA); and a fluorinated acid; a relative amount of the PAA in the composition being sufficient to ensure an etch rate of (P-doped-SiGe):(P-doped-Si) that is substantially the same as an etch rate of (N-doped-SiGe):(N-doped-Si). Such a wet-etch composition is hereafter referred to as a PAA-based etchant and can be used to make, e.g., a CMOS MBCFET, an electrode of a capacitor, etc.