Abstract: A composition for a lithium metal protective layer includes an organic solvent comprising nitromethane and dimethoxyethane, and lithium nitrate (LiNO3). A content of nitromethane is in a range from 30 wt % to 70 wt % based on a total weight of the organic solvent. In a method of fabricating a lithium electrode, a protective layer is formed on a surface of a lithium metal layer by immersing the lithium metal layer in the composition for a lithium metal protective layer.

Abstract: A method for controlling a live content broadcast includes receiving, on a first online platform, information on a first set of products registered as products for sale of a user account associated with the user terminal, and receiving from a user, as a first user input, a selection of a second set of products to sell in the live content broadcast on a second online platform among the first set of products.

Abstract: A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity.

Abstract: A method of fabricating a semiconductor device is provided. The method of fabricating the semiconductor device includes etching a stack structure to form a first trench on a first side of a dummy gate on a stack structure a second trench on a second side of the dummy gate opposite to the first side of the dummy gate, wherein the second semiconductor layer that remain after the formation of the first and second trenches form a plurality of nanosheets, partially etching the first and second trenches to form a third trench a fourth trench, forming a first sacrificial pattern inside the fourth trench, and forming a first source/drain region inside the third trench and a second source/drain region on the top surface of the first sacrificial pattern inside the fourth trench.

Abstract: A multilayer capacitor includes a body including a dielectric layer and a plurality of internal electrodes stacked with the dielectric layer interposed therebetween and including a first conductive metal and external electrodes disposed on an external surface of the body and including a second conductive metal, wherein the ratio of internal electrodes including an alloy region of the first and second conductive metals to the plurality of internal electrodes is 40 to 80%.

Abstract: An apparatus of tilting a seat cushion of a vehicle, includes a tilting motor, a pinion gear, a sector gear, and a tilting link which perform the tilting operation of the seat cushion and exert a binding force in a tilted state of the seat cushion and are provided to be connected to both of one side and the other side of a seat cushion frame, and has two sector gears positioned on left and right sides and connected to each other by a connection bar so that, by strengthening a binding force of the front portion of the seat cushion, it is possible to secure the safety of passengers in the event of a collision.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a first device including first active regions and first to third structures thereon, and a second device including a second active region, a gate structure intersecting the second active region, and a source/drain region including a lower source/drain region on the second active region having first-type conductivity, an inter-source/drain region insulating layer on the lower source/drain region, and an upper source/drain region on the inter-source/drain region insulating layer and having second-type conductivity. The first structure includes first lower and upper impurity regions. The second structure includes a second lower impurity region having the first-type conductivity, an inter-impurity region insulating layer, and a second upper impurity region having the second-type conductivity.

Abstract: A semiconductor device is provided.

Abstract: A multilayer ceramic capacitor includes: a capacitor body comprising a dielectric layer and an internal electrode layer; and an external electrode disposed on an outside surface of the capacitor body, wherein the capacitor body includes an active portion where the dielectric layer and the internal electrode layer are alternately disposed, side margin portions disposed at both side end portions of the active portion facing each other, and bonding portions disposed between the active portion and the side margin portions, and at least one of the active portion or the side margin portions includes a barium titanate-based main ingredient including barium (Ba) and titanium (Ti), and gallium (Ga).

Abstract: A semiconductor device may include a via pattern connected to a conductive pattern on a substrate, the via pattern including a lower via pattern and an upper via pattern stacked on the lower via pattern, and a wiring line connected to the upper via pattern and extending in a second direction. The wiring line may include a same metal as the upper via pattern. A bottom width of the wiring line may be greater than a top width of the wiring line. a widths of an upper face of the lower via pattern may be equal to width of the bottom face of the upper via pattern.

Abstract: A liquid crystal display includes a first substrate including: a display area including a plurality of pixels on the first substrate, a non-display area which is disposed on an outside of the display area and in which a dummy wire is disposed on the first substrate, and an image input hole which is defined therein in the non-display area and in which an image input device is disposed, a second substrate facing the first substrate and including a display area and a non-display area corresponding to those of the first substrate, a liquid crystal layer interposed between the first and second substrates, and a sealant which is in the non-display area of the first and second substrates and seals the liquid crystal layer between the first and second substrates. The dummy wire is disposed near the image input hole.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

Abstract: A semiconductor device that includes a lower pattern extending in a first direction, a first channel pattern on the lower pattern, and includes a plurality of first sheet patterns, a second channel pattern on the lower pattern, includes a plurality of second sheet patterns and spaced apart from the first channel pattern, a first gate structure which extends around the first sheet pattern, and includes a first gate electrode and a first gate insulating film, a second gate structure which extends around the second sheet pattern, and includes a second gate electrode and a second gate insulating film, a first gate capping pattern and a second gate capping pattern. The number of first sheet patterns is different from the number of second sheet patterns, and a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A semiconductor device includes a lower pattern. A channel isolation structure and a field insulating layer contact the lower pattern. A gate structure is on the lower pattern, in contact with the channel isolation structure. A channel pattern is on the lower pattern, and includes sheet patterns, each being in contact with the channel isolation structure. A source/drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source/drain pattern. The second region of the channel isolation structure includes portions whose widths increase as a distance from a bottom surface of the field insulating layer increases.

Abstract: A photovoltaic power generation module may include a ball lens that receives a medium from the outside or outputs a medium to the outside, receives sunlight that proceeds thereto from the outside when a medium is introduced thereto, and focuses the medium on one focal point, a solar cell that is disposed at a point at which sunlight is focused by the ball lens and produces electric energy from the sunlight, a support part supporting the ball lens and the solar cell and that being rotatable in a preset direction, a first motor that moves the solar cell in a direction in which the solar cell becomes distant from or close to the ball lens, a second motor that rotates the solar cell in a direction ? on a spherical coordinate system, and a third motor that rotates the support part in a direction ? on the spherical coordinate system.