Abstract: A multilayer ceramic capacitor includes: a capacitor body comprising a dielectric layer and an internal electrode layer; and an external electrode disposed on an outside surface of the capacitor body, wherein the capacitor body includes an active portion where the dielectric layer and the internal electrode layer are alternately disposed, side margin portions disposed at both side end portions of the active portion facing each other, and bonding portions disposed between the active portion and the side margin portions, and at least one of the active portion or the side margin portions includes a barium titanate-based main ingredient including barium (Ba) and titanium (Ti), and gallium (Ga).

Abstract: A semiconductor device may include a via pattern connected to a conductive pattern on a substrate, the via pattern including a lower via pattern and an upper via pattern stacked on the lower via pattern, and a wiring line connected to the upper via pattern and extending in a second direction. The wiring line may include a same metal as the upper via pattern. A bottom width of the wiring line may be greater than a top width of the wiring line. a widths of an upper face of the lower via pattern may be equal to width of the bottom face of the upper via pattern.

Abstract: A liquid crystal display includes a first substrate including: a display area including a plurality of pixels on the first substrate, a non-display area which is disposed on an outside of the display area and in which a dummy wire is disposed on the first substrate, and an image input hole which is defined therein in the non-display area and in which an image input device is disposed, a second substrate facing the first substrate and including a display area and a non-display area corresponding to those of the first substrate, a liquid crystal layer interposed between the first and second substrates, and a sealant which is in the non-display area of the first and second substrates and seals the liquid crystal layer between the first and second substrates. The dummy wire is disposed near the image input hole.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A semiconductor device includes a first impurity region on a substrate; a channel pattern protruding from an upper surface of the substrate, the channel pattern extending in a first direction substantially parallel to the upper surface of the substrate; a second impurity region on the channel pattern, the second impurity region covering an entire upper surface of the channel pattern; a gate structure on a sidewall of the channel pattern and the substrate adjacent to the channel pattern; a first contact pattern on the second impurity region; a second contact pattern that is electrically connected to the gate structure; and a spacer between the first contact pattern and the second contact pattern. The spacer completely surrounds the second contact pattern in plan view, and the first contact pattern partially surrounds the second contact pattern in plan view.

Abstract: A semiconductor device that includes a lower pattern extending in a first direction, a first channel pattern on the lower pattern, and includes a plurality of first sheet patterns, a second channel pattern on the lower pattern, includes a plurality of second sheet patterns and spaced apart from the first channel pattern, a first gate structure which extends around the first sheet pattern, and includes a first gate electrode and a first gate insulating film, a second gate structure which extends around the second sheet pattern, and includes a second gate electrode and a second gate insulating film, a first gate capping pattern and a second gate capping pattern. The number of first sheet patterns is different from the number of second sheet patterns, and a thickness of the first gate capping pattern is different from a thickness of the second gate capping pattern.

Abstract: Provided is a semiconductor device. The semiconductor device comprises a first active pattern extending in a first direction on a substrate, a second active pattern which extends in the first direction and is adjacent to the first active pattern in a second direction different from the first direction, a field insulating film placed between the first active pattern and the second active pattern, a first gate structure which crosses the first active pattern, extends in the second direction, and includes a first gate electrode and a first gate spacer, a second gate structure which crosses the second active pattern, extends in the second direction, and includes a second gate electrode and a second gate spacer, a gate separation structure placed on the field insulating film between the first gate structure and the second gate structure.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A photovoltaic power generation module may include a ball lens that receives a medium from the outside or outputs a medium to the outside, receives sunlight that proceeds thereto from the outside when a medium is introduced thereto, and focuses the medium on one focal point, a solar cell that is disposed at a point at which sunlight is focused by the ball lens and produces electric energy from the sunlight, a support part supporting the ball lens and the solar cell and that being rotatable in a preset direction, a first motor that moves the solar cell in a direction in which the solar cell becomes distant from or close to the ball lens, a second motor that rotates the solar cell in a direction ? on a spherical coordinate system, and a third motor that rotates the support part in a direction ? on the spherical coordinate system.

Abstract: A semiconductor device includes a lower pattern. A channel isolation structure and a field insulating layer contact the lower pattern. A gate structure is on the lower pattern, in contact with the channel isolation structure. A channel pattern is on the lower pattern, and includes sheet patterns, each being in contact with the channel isolation structure. A source/drain pattern contacts the channel pattern and the channel isolation structure. The channel isolation structure includes a first region contacting the gate structure and a second region contacting the source/drain pattern. The second region of the channel isolation structure includes portions whose widths increase as a distance from a bottom surface of the field insulating layer increases.

Abstract: A semiconductor device includes a substrate having a first region and a second region, first active fins that extend in a first direction in the first region, second active fins that extend in the first direction in the second region, a first field insulating layer between the first active fins and that extend in a second direction, a second field insulating layer between the second active fins and extending in the second direction, a gate line that extends in the second direction on the second field insulating layer, the gate line linearly along with the first field insulating layer, a gate isolation layer between the first field insulating layer and the gate line, and gate spacers that extend in the second direction, the gate spacers in contact with both sidewalls of each of the first field insulating layer, the gate line, and the gate isolation layer.

Abstract: A semiconductor device includes a first and second channel separation structures extending in a first direction and spaced apart from each other in a second direction, first gate structures spaced apart from each other in the first direction between the first and second channel separation structures and in contact with the first and second channel separation structures, first and second channel patterns including first and second sheet patterns, respectively, spaced apart from each other in a third direction and in contact with the corresponding first and second channel separation structures, first and second source/drain patterns between the first and second channel separation structures, the first source/drain patterns in contact with the first channel patterns and the first channel separation structure, the second source/drain patterns in contact with the second channel patterns and the second channel separation structure, and first gate separation structures between the first and second source/drain patte

Abstract: A semiconductor device includes: a substrate, an active pattern extending in a first horizontal direction on the substrate, a plurality of nanosheets spaced apart from each other and stacked in a vertical direction on the active pattern, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region disposed on at least one side of the gate electrode on the active pattern, the source/drain region including a first layer doped with a metal, and a second layer disposed on the first layer, and an inner spacer disposed between the gate electrode and the first layer, between each of the plurality of nanosheets, the inner spacer in contact with the first layer, the inner spacer including a metal oxide formed by oxidizing the same material as the metal.

Abstract: According to a preferred embodiment of the present disclosure, a project management device includes: a division unit configured to divide a project into n construction work packages (CWPs) based on a construction type constituting the project, a minimum unit area for managing the project, and design information; and a display unit configured to classify the n CWPs according to construction statuses and work front statuses and display the n CWPs in a grid form.

Abstract: A display device includes a display panel, a support film, and a polymer layer. The display panel includes a display area comprising a first area that is bendable, and a non-display area adjacent to the display area. The support film is coupled to a bottom surface of the display panel. The support film includes a first groove overlapping with the first area. The polymer layer is disposed in the first groove. The polymer layer includes a material with higher flexibility than the support film. Angles formed by the top surface of the support film and inner sides of the support film defining the first groove are acute angles.

Abstract: A semiconductor device may include a substrate, an active pattern extended in a first horizontal direction on the substrate, a plurality of nanosheets stacked and spaced apart from each other in a vertical direction on the active pattern, a gate electrode extended in a second horizontal direction different from the first horizontal direction on the active pattern, the gate electrode surrounding the plurality of nanosheets, a source/drain region on both sides of the plurality of nanosheets in the first horizontal direction on the active pattern, a gate insulating layer between the plurality of nanosheets and the gate electrode, and a doping layer between the plurality of nanosheets and the gate insulating layer, the doping layer including silicon (Si) or silicon germanium (SiGe) and doped with a doping material, at least a portion of the doping layer overlapping an uppermost nanosheet of the plurality of nanosheets in the first horizontal direction.

Abstract: Disclosed are a dual modulator of mGluR5 and 5-HT2AR (5-HT2A receptor), and use thereof. More specifically, disclosed are a compound which acts as modulator of mGluR5 and an antagonist of 5-HT2AR at the same time, and use thereof as therapeutic agent for pain.

Abstract: A method for providing metadata sharing service may include obtaining a sharing event for a predetermined range path based on a current location of a first target object, determining whether a second original name of a second target object previously registered with a name duplicating with a first original name of the first target object according to the sharing event exists in a sharing table, generating and registering a first unique name different from a second unique name for the second original name of the second target object in the sharing table in response to the existence of a second original name previously registered with a name duplicating with the first original name, and sharing a predetermined range path based on a current location of a first target object of the first unique name according to the sharing event through a virtual drive.

Abstract: Disclosed are a dual modulator of mGluR5 and 5-HT2AR (5-HT2A receptor), and use thereof. More specifically, disclosed are a compound which acts as modulator of mGluR5 and an antagonist of 5-HT2AR at the same time, and use thereof as therapeutic agent for pain.

Abstract: According to a preferred embodiment of the present disclosure, a project management device includes: a division unit configured to divide a project into n construction work packages (CWPs) based on a construction type constituting the project, a minimum unit area for managing the project, and design information; and a display unit configured to classify the n CWPs according to construction statuses and work front statuses and display the n CWPs in a grid form.