Abstract: The tennis self-training system according to an embodiment of the present invention comprising a control device comprising recording unit configured to record a tennis game and a processor configured to analysis the tennis game based on a video obtained from the recording unit; and a ball machine unit configured to move and launch a ball according to the instructions of the control device; wherein the control device is configured to: determine the position of a player and the position of the ball machine unit based on the video, predict a falling position of the ball hit by the player based on the video, calculate a ball launch position and a ball arrival position of the ball machine unit based on the position of the player and the falling position of the ball, generate a control signal related to the ball launch position and the ball arrival position, transmit the control signal to the ball machine unit, wherein the ball machine unit is configured to: receive the control signal from the control device, move

Abstract: The tennis ball supply device according to an embodiment of the present invention includes a communication circuit configured to communicate with an external device; a launcher configured to launch a ball; a body unit configured to move the launcher; and a controller configured to: control the body unit to move to a first position, identify whether the body unit is disposed on the first position based on a signal received from the communication circuit, based on identifying that the body unit is disposed on the first position, control the launcher to launch the ball, control the body unit to move to a second position after the launcher has stopped launching the ball, and identify whether the body unit is disposed on the second position based on the signal received from the communication circuit.

Abstract: The tennis ball supply device according to an embodiment of the present invention includes a communication circuit configured to communicate with an external device; a launcher configured to launch a ball; a body unit configured to move the launcher; and a controller configured to: control the body unit to move to a first position, identify whether the body unit is disposed on the first position based on a signal received from the communication circuit, based on identifying that the body unit is disposed on the first position, control the launcher to launch the ball, control the body unit to move to a second position after the launcher has stopped launching the ball, and identify whether the body unit is disposed on the second position based on the signal received from the communication circuit.

Abstract: Provided is a phase-change memory (PCM) module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.

Abstract: Provided is a phase-change memory (PCM) module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.

Abstract: A semiconductor memory device includes a memory device, a Read-Modify-Write (RMW) controller configured to generate a merge command corresponding to at least one command among a read command and a write command which are externally provided, to receive a processing result of the merge command, and to generate a response for the at least one command corresponding to the merge command. The semiconductor memory device further includes a memory controller configured to control the memory device by receiving the merge command and to provide the processing result of the merge command to the RMW controller.

Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.

Abstract: A semiconductor device may include a media controller configured to output a write requested address when a write request to a nonvolatile memory device is provided from a host; and a cold address manager. The cold address manager may include a stack storing meta data for the write requested address, region information storage configured to manage addresses of the nonvolatile memory device with regions such that length of a region of the regions may vary after a predetermined period, a cold address detector configured to update the stack and the region information storage after the predetermined period and to detect whether an address of the nonvolatile memory device is a cold address, the cold address having write requests performed at less than a predetermined level.

Abstract: The provided is a method of controlling a dynamic random-access memory (DRAM) device comprising: storing a plurality of pieces of data consisting of a plurality of bits in a memory in a transposed manner; setting at least one refresh period for each of a plurality of rows constituting the memory; and performing a refresh operation of the memory on the basis of the set refresh period.

Abstract: A semiconductor memory device includes a memory device, a Read-Modify-Write (RMW) controller configured to generate a merge command corresponding to at least one command among a read command and a write command which are externally provided, to receive a processing result of the merge command, and to generate a response for the at least one command corresponding to the merge command. The semiconductor memory device further includes a memory controller configured to control the memory device by receiving the merge command and to provide the processing result of the merge command to the RMW controller.

Abstract: A semiconductor device may include a media controller configured to output an address in response to receiving a write request for writing to a nonvolatile memory. The semiconductor device may also include a hot address detector. The hot address detector is configured to store a list including the address output from the media controller and including meta data related to the address, to update the meta data according to the address output from the media controller, to determine whether the address output from the media controller is a hot address, and to adjust a length of the list.

Abstract: A semiconductor device may include a media controller configured to output a write requested address when a write request to a nonvolatile memory device is provided from a host; and a cold address manager. The cold address manager may include a stack storing meta data for the write requested address, region information storage configured to manage addresses of the nonvolatile memory device with regions such that length of a region of the regions may vary after a predetermined period, a cold address detector configured to update the stack and the region information storage after the predetermined period and to detect whether an address of the nonvolatile memory device is a cold address, the cold address having write requests performed at less than a predetermined level.

Abstract: A data encoder including a preprocessor configured to divide a data stream into a plurality of sub data blocks; a plurality of meta data generators each configured to generate meta data from one of the plurality of sub data blocks; and a plurality of data compressors each configured to compress one of the plurality of sub data blocks according to the meta data.

Abstract: A data encoder including a preprocessor configured to divide a data stream into a plurality of sub data blocks; a plurality of meta data generators each configured to generate meta data from one of the plurality of sub data blocks; and a plurality of data compressors each configured to compress one of the plurality of sub data blocks according to the meta data.

Abstract: A semiconductor device may include a media controller configured to output an address in response to receiving a write request for writing to a nonvolatile memory. The semiconductor device may also include a hot address detector. The hot address detector is configured to store a list including the address output from the media controller and including meta data related to the address, to update the meta data according to the address output from the media controller, to determine whether the address output from the media controller is a hot address, and to adjust a length of the list.

Abstract: A display device includes a timing controller and a data driver. The timing controller to output a first control value including information on low gray scale values, a second control value including information on high gray scale values, and a third control value including information on subfields, corresponding to input data. The data driver to control the gray scale value of a pixel in a plurality of subfields in one frame based on the first, second and third control values. The pixel is driven in an analog manner when the gray scale value based on whether the first or second control value is output, and is driven in a digital manner when the gray scale value corresponds to an emission time during a predetermined subfield among the plurality of subfields.

Abstract: A bus arbitration apparatus and method are provided. A plurality of masters may be classified into master types based on master characteristics, and bus arbitration may be performed. Thus, it is possible to prevent a bus from being distributed to a predetermined master, and it is possible to improve overall performance of a bus system by solving a problem of unbalanced distribution of performance between the plurality of masters.

Abstract: A fault indicator for indicating the occurrence of a rapid pressure surge within a housing of an electrical device has: a barrel capable of being mounted in an aperture of the housing; an actuating mechanism having a chamber with at least one orifice communicating between interior and exterior surfaces of the chamber within the housing and an actuating member movable in response to a pressure differential between the interior and exterior surfaces of the chamber; a plunger within the bore of the barrel biased outwardly in the barrel and normally retained in an armed position by the actuating member; and a radial seal disposed between the plunger and the barrel. When the pressure differential exceeds a positive threshold value, the actuating member is moved and thereby permits the plunger to move outwardly into a triggered position. The radial seal may be a dual-lip seal.

Abstract: A display device includes a timing controller and a data driver. The timing controller to output a first control value including information on low gray scale values, a second control value including information on high gray scale values, and a third control value including information on subfields, corresponding to input data. The data driver to control the gray scale value of a pixel in a plurality of subfields in one frame based on the first, second and third control values. The pixel is driven in an analog manner when the gray scale value based on whether the first or second control value is output, and is driven in a digital manner when the gray scale value corresponds to an emission time during a predetermined subfield among the plurality of subfields.

Abstract: An apparatus for measuring ganglion cells may include: a light generation unit configured to irradiate a first light signal polarized in a first direction and a second light signal polarized in a second direction perpendicular to the first direction to a subject; a reflected light processing unit configured to generate an amplification signal corresponding to an image of the subject using a first reflection signal, which is the first light signal reflected from the subject, and a second reflection signal, which is the second light signal reflected from the subject; and an image processing unit configured to measure ganglion cells in the subject using the amplification signal. The apparatus may be used to count the number of normal ganglion cells in the retina by measuring a phase difference of two lights polarized in different directions. The apparatus may also be used to monitor the progress of glaucoma.