MITIGATING WRITE DISTURBANCE ERRORS OF PHASE-CHANGE MEMORY MODULE
Provided is a phase-change memory (PCM) module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.
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This application claims priority to and the benefit of Korean Patent Application No. 10-2021-0042919, filed on Apr. 1, 2021, the disclosure of which is incorporated herein by reference in its entirety.BACKGROUND 1. Field of the Invention
The present invention relates to a phase-change memory (PCM) module.2. Discussion of Related Art
Due to the expansion of server system technology for supporting high performance computing and an increase in demand for storage capacity, phase-change memories (PCMs) are attracting attention as next-generation non-volatile memories (NVMs) which satisfy the requirements.
However, a write disturbance error (WDE) is a serious problem of reliability which hinders commercialization of PCMs. The WDE occurs at neighboring cells of a written cell due to heat emission.
Existing research for preventing a WDE is based on a write cache or verify-and-correction but is inappropriate for high performance computing due to significant area overhead and performance degradation. Accordingly, an on-demand correction is necessary to minimize performance overhead.
PCMs are attracting attention as NVMs for replacing existing dynamic random access memory (DRAM)-based main memory systems or introducing a new storage-class memory layer between a DRAM and a storage. Recently, software-defined memories have been proposed to use NVMs as high-speed storages or expanded main memories interchangeably on user-level applications.
On the other hand, applications of in-memory database require data to be retained with a lower latency time in persistent memories. PCMs are proposed as a suitable candidate for solving this problem.
Also, PCM-based products are tested in various environments for performance evaluation and exploration of suitable applications thereof. Accordingly, utilizing and enhancing the PCM-related technology is important in achieving a low-latency and large-scale memory system in the future.
Even though PCMs have attractive characteristics, it is not fully commercialized due to lower cell reliability than DRAMs. In particular, there are several kinds of reliability issues in PCMs, such as cell endurance, resistance drift, and read/write disturbance.
WDEs are one of the major problems which delay the massive commercialization of PCMs. WDEs are defined as an interference problem on adjacent cells similar to row-hammer in DRAM devices. However, unlike DRAM row-hammer, a WDE specially occurs on an idle cell near a cell under RESET and is the problem of changing the state of an idle cell and reading an incorrect value.
In addition, a widely-used application, such as in-memory database, directly stores data in NVMs which heavily utilize cache-line flush commands. This kind of application may incur frequent write operations on PCMs and thereby makes cells vulnerable to WDEs. Existing techniques for mitigating WDEs, such as Data encoding based INsulation technique (DIN), Lazy correction, and Architecture for write DisturbAnce Mitigation (ADAM), are built on the top of verify-and-correction (VnC), which significantly degrades performance and consequently hinders the implementation of a high performance computing platform.
Meanwhile, a solution for WDEs, the write cache-based method, rarely considers the size limit of a supercapacitor which is required for data flush on a system crash or failure (hold-up time up to 100 μs for commercial devices).
To avoid these disadvantages (i.e., performance degradation and additional hardware resource), the present invention proposes a low-cost in-module disturbance barrier (IMDB).
Related arts are built upon the probability-based WDE trigger model which incurs WDEs for specific probabilities. However, it has been recently reported that the WDE occurs when the cells are exposed to a RESET operation for a specific time. Unlike the related arts, according to the present invention, the number of 1-to-0 bit flips (i.e., the number of RESETs) is recorded. Accordingly, most of the WDE-vulnerable data may be rewritten right before 1-to-0 bit flips reach the disturbance limitation.
Most data is recorded not only in a static random access memory (SRAM)-based table to manage more write addresses but also in a smaller supercapacitor area required for a system failure, except for a higher-tier second table named barrier buffer, to minimize additional hardware resources. Meanwhile, if the replacement policy merely considers an entry holding a smaller number of 1-to-0 flips as an eviction candidate, temporal locality would be overlooked.SUMMARY OF THE INVENTION
The present invention is directed to providing a phase-change memory (PCM) module for reducing write disturbance errors (WDEs).
Specifically, the present invention is directed to solving WDEs of a phase-change random access memory (PRAM) by estimating addresses vulnerable to interference from a WDE limitation number and restoring a state of data allocated to the addresses unlike a related art of encoding a data pattern or determining whether an error occurs in every read operation.
According to an aspect of the present invention, there is provided a PCM module including a PCM device including a bit line and a word line, a memory controller configured to output a command related to an operation of the PCM device, and an interference mitigation part located between the memory controller and the PCM device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.
The above and other objects, features and advantages of the present invention will become more apparent to those of ordinary skill in the art by describing exemplary embodiments thereof in detail with reference to the accompanying drawings, in which:
Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the embodiments. However, the present invention can be embodied in various different forms and is not limited to the drawings and embodiments disclosed below. To clearly describe the present invention, parts unrelated to the present invention are omitted. Throughout the drawings, like reference numerals refer to like elements.
First, the concept of a phase-change memory (PCM) will be described below.
As shown in
For reference, the interference mitigation part 102 may be defined as an in-module disturbance barrier (IMDB).
Specifically, the interference mitigation part 102 may include at least one of a main table for storing the accumulated number of rewrite operations and the accumulated number of calculated flips, a buffer table for storing data related to a command to be rewritten, and an Approximate Lowest number Estimator (AppLE) for sampling one group from a plurality of table entries to minimize a cycle consumed by a replacement policy of the main table and the buffer table.
Specifically, the data structure of each entry included in the main table may include at least one of an address variable (Row & Col) which represents an address corresponding to a command, a rewrite control variable (RewriteCntr) which is increased by a preset value every time a rewrite operation is performed by the interference mitigation part 102, a zero flip control variable (ZeroFlipCntr) which represents the accumulated number of 1-to-0 flips, and a max zero flip control variable (MaxZFCidx) which represents an index corresponding to the largest one of zero flip control variables.
In an exemplary embodiment, when the zero flip control variable of one entry exceeds the preset threshold value, the interference mitigation part 102 may perform a rewrite operation for the entry.
Meanwhile, when a rewrite operation is performed for one command, the interference mitigation part 102 may record data corresponding to the command in the main table to the buffer table.
Here, the data structure of an entry included in the buffer table may include at least one of an address variable in which the address variable in the main table is transferred and stored, a rewrite control variable in which the rewrite control variable in the main table is transferred and stored, a command variable which stores the command, and a frequency control variable (FreqCntr).
Also, the AppLE may define a certain number of main table entries as one group and perform a replacement policy for the main table by applying the defined group as one unit cycle.
In other words, the AppLE may set a random offset for each of the defined groups and perform a read operation on entries included in the defined group on the basis of the set offset.
Meanwhile, the main table and the buffer table may include two sets of static random access memories (SRAMs).
For example, the main table may include a first SRAM and a second SRAM.
Here, the first SRAM may index an entry of the main table and may be allocated to an address variable in the main table, and the second SRAM may be allocated to a zero flip control variable, a max zero flip control variable, and a rewrite control variable in the main table.
A detailed overview of the PCM device of an 8 gigabyte (GB) module is illustrated in
The device includes eight subarrays, and each subarray includes eight mats (8K word lines and 4K bit lines for each mat). First, main word line drivers activate a subarray in each bank, and a row address is commonly fed into sub-word line drivers (SWDs) in the activated subarray to select a row which carries 4 KB data. Subsequently, the selected 4 KB data is sensed by bit line sense amplifiers (BLSA) and transferred through global bit lines (shaded arrow in
The output procedure implies that eight consecutive bit lines constitute one column. Finally, when eight data pins per device are assumed as shown in
For a write operation, data on write drivers (W/D) are written back to the cell array with differential write. Herein, it is assumed that the columns are well insulated from each other. Accordingly, the neighboring columns do not incur write disturbance errors (WDEs). Otherwise, four or more read operations are required for each write operation when verify-and-correction (VnC) is adopted, and thus the overhead of baseline design is reduced as well. In addition, since the material of the PCM is configured to overlap a bit line, WDEs mainly occur on adjacent materials which are patterned on the same bit line.
Modeling of write disturbance in the PCM will be described below.
WDEs hinder the popularization of a device which shifts the resistance of a cell in the amorphous state to the crystalline state. As shown in
In the present invention, for convenience of description, it is assumed that a disturbance limitation number is 1K (i.e., a WDE occurs when a cell is exposed to a 1K number of 1-to-0 flips on neighbors).
For reference, various studies aimed at reducing WDEs in the PCM are under way.
First, VnC is the most naive and rigid method to reduce WDEs. Two pieces of neighbor data are read for verification before data writing. Subsequently, the data is read again after the data is written. When a WDE occurs, correction is performed. Although it is an effective WDE mitigation method, significant performance overhead is induced by four more read operations for each write operation (including correction).
According to a related art, lazy correction is built on the top of an error correction pointer (ECP) chip, and locations of disturbed cells are temporarily stored in the ECP. Accordingly, the correction may be deferred to be as late as possible until the ECP becomes full within a super-dense PCM module (SD PCM). However, lazy correction requires one additional device which has larger process technology than normal devices. Since VnC-based approaches incur considerable performance overhead, some methods have been proposed to reduce WDE vulnerable patterns by utilizing data encoding. Accordingly, less or no VnC is necessary.
A Data encoding based INsulation technique (DIN), which is another existing method, proposes a codebook which encodes continuous 0s in a compressed cache line as “01” or “10” patterns. Accordingly, the DIN may eliminate disturbance vulnerable patterns as much as possible. However, the encoded data needs to be in the range of the length of the cache line (i.e., 512 bits). Otherwise, the DIN falls back to the VnC method, and thus performance is significantly degraded.
MinWD, which is another existing method, encodes write data into three candidates with special shift operations and selects the most aggressive encoding form among candidates. However, the encoding methods generally require support of multi-bit error correction code, which is unaffordable in general client nodes, unlike a server side.
An architecture for write DisturbAnce Mitigation (ADAM), which is another existing method, compresses a cache line with the frequent pattern compression (FPC) and aligns the line to the right and left alternatively. Accordingly, adjacent cells holding valid data bits are reduced greatly. However, the compressed word is still vulnerable to WDEs when the length of the compressed word is longer than 50% of the original data length. Data caches are used to increase throughput of a system. However, data caches also can be utilized to reduce WDEs by temporarily storing frequently written data into the more reliable volatile region such as SRAM.
A sparse-insertion write cache (SIWC), which is another existing method, utilizes a write cache for absorbing bit flips to reduce WDEs. The SIWC utilizes a probabilistic method, coin tossing, to evict data from the write cache and insert new data with certain probabilities. Since most of the data in which a WDE may easily occur is stored in the write cache, victims of WDEs become secure. However, this method introduces several megabytes of volatile memory to obtain a higher hit ratio. Furthermore, even when the write cache is embedded in the memory module, a supercapacitor for data flush on a system failure needs to be expanded as the volatile region enlarges. Generally, a commercial non-volatile dual in-line memory module (NVDIMM) ensures that volatile data needs to be flushed within 100 μs. Accordingly, it is necessary to reduce the write cache size to a more practical value while sufficiently utilizing disturbance-vulnerable write patterns. Moreover, it is reported that WDEs likely occur when cells are exposed to RESET for specific times. Accordingly, using this information is important to markedly reduce WDEs.
An IMDB according to the present invention will be described below.
First, the overall system of an IMDB is as follows.
The IMDB module proposed by the present invention is present between the media controller and the PCM. The IMDB module includes the main table, a barrier buffer, and a finite state machine which controls entry migration between two tables. Data flip patterns of write commands in this module are managed to trigger rewriting WDE-vulnerable addresses before the occurrence of a WDE instead of being based on VnC. The introduction of IMDB induces variable latencies during the transaction. However, the iMC in the processor may communicate via a double data rate transactional (DDR-T) protocol and thus allows variable latencies as in commercial persistent memory products.
First, the main table of the IMDB is implemented with a set of SRAMs. Accordingly, the IMDB may read or write only one entry at a time in which the content of the entry is updated through the control logic. Also, data is not stored in the main table to save power spent on supercapacitors. Specifically, four major fields are used to estimate the degree of WDE of a written address.
- Row & Col: This contains row and column addresses in a bank which is currently managed in the main table.
- ZeroFlipCntr: Eight sub-counters are in this field, each of which calculates the number of bit flips from 1 to 0 and manages each 64-bit data in a 64 B cache line.
- MaxZFCIdx: This indicates the maximum sub-counter of ZeroFlipCntr which is updated in the control logic after an entry is read. This is used to instantly compare the maximum value of ZeroFlipCntr with the threshold value for rewrite operations.
- RewriteCntr: An eight-bit counter represents the frequency of rewrite operations on the address of Row & Col.
Since only one entry is accessible at a time, it is necessary to take resource contention on the IMDB into consideration. This problem is resolved by building a finite state machine having 3 states, that is, IDLE, HIT, and MISS, which represent the availability of the main table, in the control logic. A new command is not started by the IMDB when the state is not in IDLE. In other words, the main table is unavailable. After a command is inserted into one of the IMDBs from the media controller, the IMDB operates in two different ways regardless of whether an address is found in the table.
- When an address is found in the main table, the state is shifted to HIT. Meanwhile, both newly and previously written pieces of data are passed to the control logic, and the number of 1-to-0 bit flips is updated by a dedicated 1-to-0 counter of the control logic. The number is accumulated in the corresponding ZeroFlipCntr. When the maximum value of ZeroFlipCntr surpasses the predefined threshold, two rewrites on adjacent word lines are generated and sent to the write queue in the media controller. Meanwhile, the value of RewriteCntr increases. Since system stability is important, the highest priority is given to the rewrite request.
- When an address is not found in the main table, an insertion is required while the state is shifted to MISS. A probabilistic insertion method is used herein. According to the present invention, infrequent accesses are filtered out with a probability p to reduce evictions from the SRAM. When an insertion is required, a victim (will be described below) is determined according to the replacement policy defined herein, and thus a new entry can replace the victim entry.
In addition, it is necessary to determine two parameters, a threshold value of generating a rewrite command and an insertion probability p. First, the threshold value is determined according to a WDE limitation number. Since two word lines may disturb a word line, the threshold value is determined as a half of the WDE limitation number. Since the WDE limitation number of 1K is assumed herein, threshold value=511. Accordingly, the bit width of each ZeroFlipCntr becomes 9. With regard to the insertion probability p, a large value incurs frequency entry evictions, whereas a small value may skip a rewrite process even after a word line reaches the WDE limitation. According to the present invention, most of the malicious attacks may be detected for all benchmarks derived from various experiments, and thus p is assumed to be 1/128.
Next, the barrier buffer is described.
The barrier buffer which is a higher-tier table is utilized to store an address, and data frequently experiences 1-to-0 bit flips as shown in
As shown in
On the other hand, the data of the LFU entry is sent back to the media controller so that the dirty data may be written back, and the information of the LFU entry is demoted to the entry of the main table at which the promoted entry has been present. As a result, the barrier buffer only stores frequently flipped data. Accordingly, WDEs can be further reduced. Since the barrier buffer may function concurrently with the main table, the latency time may be hidden.
In practice, both the main table and the barrier buffer in the IMDB are implemented as two sets of SRAMs. For the main table, two types of SRAMs are used. First, a dual-port content-addressable memory (CAM)-based SRAM is allocated as Row & Col fields to index entries in the table. On the other hand, a multi-port SRAM including ZeroFlipCntr, MaxZFCIdx, and RewriteCntr has one write port for updating content and multiple read ports for obtaining entry information at a time to apply the proposed replacement policy. Accordingly, the number of read ports is the same as the number of entries in the table. However, the next subsection shows that the number of read ports may be reduced by adopting the AppLE. For the barrier buffer, a dual-port CAM-based SRAM and a dual-port SRAM are assigned for Row & Col and data & RewriteCntr & FreqCntr, respectively. The burden of energy consumption is negligible because only a small number of entries in the barrier buffer are enough to provide high WDE mitigation performance as described below. It is to be noted that the valid bits are merely implemented as registers for directly probing status. The media controller is modified slightly to support the IMDB. First, previously written data needs to be collected in advance to calculate the number of bit flips. Accordingly, a prewrite read operation is required to get the previously written data. The controller has one or more data buffers to transfer the previous data, and an additional bit is required to distinguish prepared commands from unprepared commands (referred to as “prepared”). A prewrite read request is generated ahead of a write request. The prewrite read request has a higher priority than write requests but a lower priority than normal read requests. Since write requests in the media controller are drained when the write queue becomes full, a long idle time remains between the reading and writing data from/to the PCM media. In addition, a merge operation of write requests is introduced. In the merge operation, a rewrite operation is merged with existing write requests for the same address. Since a rewrite operation entirely writes all bits of data, excessive rewrites may continuously incur cascaded WDEs on neighbor lines. Therefore, when rewrite requests are integrated with existing requests in the queue, WDEs may be further reduced.
SIWC described as a related art requires 256×64 B=32 KB of SRAM for each PCM bank (when 256 addresses are managed).
On the other hand, in the method according to the present invention, the main table entry has 108 bits (=25 b+8 b+72 b+3 b), and the barrier buffer entry has 553 bytes (=64 B+25 b+8 b+8 b) (see
Therefore, the proposed method requires 256×108 b≈3.4 KB of SRAM for the main table per PCM bank, and the barrier buffer consumes 8×553 b≈0.6 KB of SRAM per PCM bank (see description below). Consequently, (3.4 KB+0.6 KB)×4 bank=16 KB of SRAM is converted into 2 KB per 1 GB of PCM.
A replacement policy will be described below.
A replacement (or eviction) policy for managing WDEs in a limited table according to disturbance-vulnerable is required. The least recently used (LRU) policy is a representative management policy which keeps tracks of the recency of access information in a constrained data structure. However, a WDE occurs when a cell is overly flipped. Accordingly, it is necessary to manage the frequency of 1-to-0 flips and select a replacement entry according to the corresponding information. In summary, a replacement policy which utilizes the knowledge of disturbance-vulnerable pattern in a limited table is necessary to evict vulnerable address information. A replacement policy is defined herein by utilizing ZeroFlipCntr and RewriteCntr. The former shows the degree of interference to adjacent word lines presently, and the latter declares the degree of interference to adjacent word lines historically as briefly described above. When the corresponding entry is not found and the input command demands a new entry in the main table which is fully occupied, the policy is ready to select a victim entry. The minimum number of ZeroFlipCntr is firstly extracted from the main table as a victim candidate because this is a less urgent aggressor presently. However, two or more victim candidates may exist due to the same value of ZeroFlipCntr. The aggressiveness of incurring WDEs may vary depending on RewriteCntr which is write information. Accordingly, an entry holding the minimum number of RewriteCntr is finally selected as a replacement entry.
The proposed replacement policy utilizes the knowledge of the disturbance-vulnerable patterns, that is, ZeroFlipCntr and RewriteCntr, well. However, the proposed policy ignores the “warm-up” phase of entries in the table. Since the policy prioritizes the present vulnerability (e.g., ZeroFlipCntr) to restore urgent data on demand, a recently inserted but insufficiently baked entry may be easily evicted from the main table. Although RewriteCntr contains the historical knowledge of WDEs, the knowledge is not useful when a corresponding entry is unluckily pushed out of the list by other addresses after being newly inserted.
As shown in
A lowest number estimator will be described below.
The eviction policy requires a multi-port SRAM and a set of comparators to obtain a victim entry among all entries. Here, the number of ports or read ports on the SRAM equals the number of entries. However, when the number of read ports increases, all of a latency time, an area, and energy increase (see
All of the modules described above are bound as a single module below, and a toy example is described. The example assumes that row and column addresses are as follows.
In this example, a target address which incurs a WDE on neighbors is assumed to be eight bits as 0xBEEF. Here, the row address and the column address are 0xBE and 0xEF, respectively. Two bytes of data are transferred by a write command, and a single ZeroFlipCntr manages all data. Each of the main table and the barrier buffer includes four entries. Data preparation. The media controller receives a write command from the processor iMC and read data already stored in the PCM device to prepare to calculate 1-to-0 flips in the IMDB (1). Once previous data arrives through the read phase of the media controller (2), the command is issued to the IMDB along with new and previous data (3). Filling the main table. When the command in the previous operation arrives, the control logic decomposes the command address into row and column addresses to determine whether the command is a hit or a miss on the tables. In this case, misses occur both on the barrier buffer and the main table. However, the main table has a vacant space for the input command. In other words, the command information may be directly stored in the table by simply validating an entry instead of replacing the entry (4). As described above, the number of zeros in the write data is recorded in ZeroFlipCntr to prevent early eviction from the table without a “warm-up” period. When subsequent commands access the same address, 1-to-0 flip counts are calculated and added to the current ZeroFlipCntr (5). Replacement on the main table. When the main table is full and there is no entry available for the next input command, it is necessary to select a victim candidate and make room for the input command OxBEEF. As shown in the drawing, the entry storing the information of 0xDEAD has the smallest number of ZeroFlipCntr among all entries calculated from the AppLE (6). Accordingly, all information of 0xDEAD is replaced by 0xBEEF concurrently (7). When repetitive writing to 0XBEEF with a frequent number of 1-to-0 flips causes ZeroFlipCntr to reach the threshold value, rewrite commands on neighboring lines (i.e., 0xBDEF and 0xBFEF) are generated and sent back to the media controller (8). Meanwhile, the barrier buffer selects a victim entry and demotes the victim entry to the main table. Also, an eviction command is generated on the basis of the victim entry and sent back to the media controller (9). After both the demoted entry and an entry incurring the rewrite operation (i.e., entry promotion) are read out from the table, the entries are interchangeably stored in the main table and the barrier buffer. Specifically, the promoted entry is stored with the write data to prevent a WDE (10).
As shown in
Design parameters, specifically the number of entries Nmt in the main table, the number of entries in the barrier buffer Nb, and the number of read ports Ng (e.g., group size) dedicated to the AppLE, are important in the following case: realizing a cost-effective architecture for the proposed method. The trade-off function of the proposed method may be defined using Equation 1 below. Here, W, A, and S denote the number of WDEs, the area, and the speedup, respectively.
T=W(Nmt, Nb, Ng)+A(Nmt, Nb, Ng)+S−1(Nb, Ng) [Equation 1]
As described above, the area consumed by an SRAM may shrink noticeably from Ng=32 (see
T=W(Nmt, Nb, Ng)+A(Nmt, Nb)+S−1(Nb, Ng),
- where Ng≤32, Nb≤64
According to Equation 2, the effectiveness of the prior knowledge is evaluated, and the appropriate size Nmt of the main table is determined. Subsequently, sensitivity analyses are performed on the number of entries in the barrier buffer Nb and the group size for the AppLE Ng to determine the cost-effective parameters. Finally, these parameters are applied and compared with those in previous studies to show the performance of the proposed method.
The barrier buffer, which is a small table containing data frequently flipped from 1 to 0, is expected to yield fewer WDEs.
Sensitivity analysis on the AppLE will be described below.
The AppLE is proposed to reduce the number of read ports on an SRAM for the replacement policy. Therefore, a sensitivity analysis with respect to the group size, which is regarded as the number of read ports on the SRAM, is required because the proposed method is a randomized approach. For a straightforward analysis, the barrier buffer is not applied in this evaluation. Also, the group size begins from 32 due to the feasibility of this value in a practical system.
As described above, the group size for the AppLE and the numbers of entries in the main table and the barrier buffer are suitably determined in consideration of the trade-off analyses. The method proposed in the present invention will be compared with the related arts.
The cost-effective architecture of the proposed method includes 256 entries in the main table and eight entries in the barrier buffer with a group size of eight, and the group size of four is denoted as IMDB. (e256b8g4) is associated with a more aggressive reduction in the number of read ports on the SRAM.
The present invention proposes an on-demand table-based method for reducing WDEs within a PCM module. The proposed method utilizes SRAM tables to manage variations of write data, by which highly vulnerable addresses are rewritten. The present invention declares that the table-based method requires a dedicated replacement policy, and prior knowledge of zeros in write data can enhance the WDE mitigation performance. Subsequently, the AppLE efficiently reduces the number of read ports on SRAMs required for the proposed policy to reduce both the area and energy overhead incurred by the overloaded multi-port SRAMs. The present invention also shows that the LRU policy and the fully randomized replacement policy are less reliable than the proposed method. On the other hand, a small amount of the SRAM absorbs additional bit flips and allows offloading of supercapacitor burden required for system failures. Consequently, some rigorous sensitivity analyses concerning design parameters are performed to obtain a cost-effective architecture. According to the analysis, the proposed work can reduce WDEs by 1218 times, 439 times, and 202 times compared to ADAM, lazy correction, and SIWC-entry, respectively, while maintaining the operation speed and energy consumption which are almost similar to those of the baseline.
According to the present invention, it is possible to markedly reduce WDEs without appreciable slowdown and additional energy consumption compared to the related art.
Also, according to the PCM module proposed by the present invention, it is possible to easily evict insufficiently baked addresses which can incur WDEs in other cells.
The experimental results indicate that the proposed method reduces WDEs by 1,218 times, 439 times, and 202 times respectively in comparison with ADAM, lazy correction, and SIWC-entry with negligible speed degradation.
In particular, according to the present invention, it is possible to implement a low-cost on-demand rewrite method supported by a two-tier SRAM in order to reduce WDEs. This is the first attempt of on-demand approach based on a more practical WDE trigger model to reduce WDEs.
1. A phase-change memory module comprising:
- a phase-change memory device including a bit line and a word line;
- a memory controller configured to output a command related to an operation of the phase-change memory device; and
- an interference mitigation part located between the memory controller and the phase-change memory device and configured to perform a rewrite operation on the basis of a state transition characteristic of the command output from the memory controller.
2. The phase-change memory module of claim 1, wherein the interference mitigation part calculates a number of 1-to-0 flips of the command and performs a rewrite operation for the command when the calculated number of 1-to-0 flips exceeds a preset threshold value.
3. The phase-change memory module of claim 2, wherein the interference mitigation part includes:
- a main table that stores an accumulated number of rewrite operations and an accumulated number of calculated flips;
- a buffer table that stores data related to a command to be rewritten; and
- an approximate lowest number estimator that samples one group from a plurality of table entries to minimize a cycle consumed by a replacement policy of the main table and the buffer table.
4. The phase-change memory module of claim 3, wherein a data structure of each entry included in the main table includes at least one of:
- an address variable (Row & Col) in which an address corresponding to the command is stored;
- a rewrite control variable (RewriteCntr) which is increased by a preset value every time a rewrite operation is performed by the interference mitigation part;
- a zero flip control variable (ZeroFlipCntr) in which the accumulated number of 1-to-0 flips is recorded; and
- a max zero flip control variable (MaxZFCidx) in which an index corresponding to a largest one of zero flip control variables is recorded.
5. The phase-change memory module of claim 4, wherein, when the zero flip control variable of one entry included in the main table exceeds the threshold value, the interference mitigation part performs a rewrite operation for the entry.
6. The phase-change memory module of claim 4, wherein, when a rewrite operation is performed for the command, the interference mitigation part records data corresponding to the command in the main table to the buffer table, and
- a data structure of entries included in the buffer table includes at least one of:
- an address variable in which the address variable in the main table is transferred and stored;
- a rewrite control variable in which the rewrite control variable in the main table is transferred and stored;
- a command variable which stores the command; and
- a frequency control variable (FreqCntr).
7. The phase-change memory module of claim 3, wherein the approximate lowest number estimator defines a certain number of main table entries as one group and performs a replacement policy for the main table by applying the defined group as one unit cycle.
8. The phase-change memory module of claim 7, wherein the approximate lowest number estimator sets a random offset for each defined group and performs a read operation on the entries included in the defined group on the basis of the set offset.
9. The phase-change memory module of claim 3, wherein the main table and the buffer table include two sets of static random access memories (SRAMs).
10. The phase-change memory module of claim 8, wherein the main table includes a first SRAM and a second SRAM,
- wherein the first SRAM indexes the entry of the main table and is allocated to an address variable of the main table, and
- the second SRAM is allocated to a zero flip control variable, a max zero flip control variable, and a rewrite control variable of the main table.
Filed: Jul 9, 2021
Publication Date: Oct 6, 2022
Applicants: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION (Seoul), Foundation for Research and Business, Seoul National University of Science and Technology (Seoul)
Inventors: Hyun KIM (Seoul), Hyo Keun LEE (Seoul), Seung Yong LEE (Seoul), Hyuk Jae LEE (Gyeonggi-do)
Application Number: 17/371,872