Abstract: Disclosed is a small animal intraventricular injection compensator for injecting a drug into a desired location through a syringe, the compensator including: a guide part provided with a guide hole into which a needle of a syringe is inserted; a body comprising an upper cavity provided inside thereof and a cradle provided to seat the guide part on an upper side thereof; and a fixation part integrally provided with the body or separately provided, and comprising a lower cavity provided to allow a head accommodation space, which a head of a small animal may enter into or exit from, to be provided inside thereof by corresponding to the upper cavity.

Abstract: A semiconductor device including a variable resistance device is provided. A variable resistance element according to one embodiment of the present disclosure includes: an ion-receiving layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the sidewall of the ion-receiving layer; a gate pattern connected to an outer sidewall of the ion supply layer; and a source pattern connected to one of the top or bottom of the ion-receiving layer, and a drain pattern connected to the other one of the top or bottom of the ion-receiving layer, wherein a resistance of the ion-receiving layer varies depending on an amount of ions supplied from the ion supply layer based on a voltage applied to the gate pattern.

Abstract: A nonvolatile memory device includes a substrate, a source electrode structure disposed on the substrate, a channel structure disposed to be contact a sidewall surface of the source electrode structure, a resistance change memory layer disposed on a sidewall surface of the channel structure, a drain electrode structure disposed to contact the resistance change memory layer, a plurality of gate dielectric structures extending in the first direction and disposed to be spaced apart from each other in a second direction, and a plurality of gate electrode structures disposed to extend in the first direction in the plurality of the gate dielectric structure.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a gate line structure disposed over the substrate, a gate dielectric layer covering one sidewall surface of the gate line structure and disposed over the substrate, a channel layer disposed to cover the gate dielectric layer and disposed over the substrate, a bit line structure and a resistance change structure to contact different portions of the channel layer over the substrate, and a source line structure disposed in the resistance change structure. The gate line structure includes at least one gate electrode layer pattern and interlayer insulation layer pattern that are alternately stacked along a first direction perpendicular to the substrate, and extends in a second direction perpendicular to the first direction.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate, a resistance change layer disposed over the substrate, a gate insulation layer disposed on the resistance change layer, a gate electrode layer disposed on the gate insulation layer, and a first electrode pattern layer and a second electrode pattern layer that are disposed respectively over the substrate and disposed to contact a different portion of the resistance change layer.

Abstract: A nonvolatile memory device includes a substrate having an upper surface and a channel structure disposed over the substrate. The channel structure includes at least one channel layer pattern and at least one interlayer insulation layer pattern, which are alternately stacked in a first direction perpendicular to the upper surface, and the channel structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a resistance change layer disposed over the substrate and on at least a portion of one sidewall surface of the channel structure, a gate insulation layer disposed over the substrate and on the resistance change layer, and a plurality of gate line structures disposed over the substrate, each contacting a first surface of the gate insulation layer and disposed to be spaced apart from each other in the second direction.

Abstract: A semiconductor device including a variable resistance device is provided. A variable resistance element according to one embodiment of the present disclosure includes: an ion-receiving layer having a top, a bottom and a sidewall connecting the top to the bottom; an ion supply layer having an inner sidewall connected to at least a portion of the sidewall of the ion-receiving layer; a gate pattern connected to an outer sidewall of the ion supply layer; and a source pattern connected to one of the top or bottom of the ion-receiving layer, and a drain pattern connected to the other one of the top or bottom of the ion-receiving layer, wherein a resistance of the ion-receiving layer varies depending on an amount of ions supplied from the ion supply layer based on a voltage applied to the gate pattern.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, and a gate structure disposed over the substrate. The gate structure includes at least one gate electrode layer pattern and at least one gate insulation layer pattern, which are alternately stacked along a first direction perpendicular to the upper surface. The gate structure extends in a second direction perpendicular to the first direction. The nonvolatile memory device includes a ferroelectric layer disposed on at least a portion of one sidewall surface of the gate structure. The one sidewall surface of the gate structure forms a plane substantially parallel to the first and second directions. The nonvolatile memory device includes a channel layer disposed on the ferroelectric layer, and a source electrode structure and a drain electrode structure disposed to contact the channel layer and spaced apart from each other in the second direction.

Abstract: A nonvolatile memory device according to an embodiment includes a substrate having an upper surface, a source electrode structure disposed on the substrate, and a channel structure disposed over the substrate and disposed to contact one sidewall surface of the source electrode structure. In addition, the nonvolatile memory device includes a drain electrode structure disposed to contact one sidewall surface of the channel structure over the substrate. In addition, the nonvolatile memory device includes a plurality of ferroelectric structures extending in a first direction perpendicular to the substrate in the channel structure and disposed to be spaced apart from each other along the second direction perpendicular to the first direction. In addition, the nonvolatile memory device includes a gate electrode structure disposed in each of the plurality of ferroelectric structure to extend along the first direction.

Abstract: A system is provided for evaluating vehicle performance. The system includes a function system model that models an operation of a function system of a vehicle and an operation of which is determined based on a control signal output from a controller within the vehicle. Additionally, the system includes a dynamic model configured to model a behavior of the vehicle based on the operation of the function system model.

Abstract: A system of modeling an anti-lock brake system (ABS) controller of a vehicle includes: a vehicle speed estimation network configured to estimate a vehicle speed through machine learning using wheel speed data of each of a plurality of wheels of the vehicle; a wheel speed state estimation network configured to estimate a time series characteristic of the wheel speed through machine learning using information on the wheel speed data and information on whether a brake pedal is depressed; and a classification network configured to estimate a braking mode for controlling an increase, a decrease, or steady state of a braking pressure of each wheel through machine learning using speed estimation data of the vehicle estimated by the vehicle speed estimation network and time series characteristic estimation data of the wheel speed estimated by the wheel speed state estimation network.

Abstract: A cathode active material for a lithium secondary battery includes a lithium-aluminum-titanium oxide formed on a surface of a lithium metal oxide particle having a specific formula. The cathode active material may have an improved structural stability even in a high temperature condition.

Abstract: Provided is a porous lithium composite phosphate-based compound containing lithium and having open pores formed in primary particles. As the open pores are formed in the primary particles themselves, a contact area between an electrolyte and the lithium composite phosphate-based compound is maximized, and low conductivity is compensated for, such that a diffusion rate of lithium ions is remarkably increased, and when the lithium composite phosphate-based compound is used as an active material of a secondary battery, the secondary battery may be charged and discharged at a high speed. Additionally, there are advantages in that an electrode density may be significantly increased in addition to the increase in the diffusion rate of the lithium ions, and charge and discharge cycle characteristics may be significantly stable.

Abstract: The present invention relates to a peptide for inhibiting bone resorption and, more specifically, to a peptide for inhibiting bone destruction by inhibiting the differentiation and activity of osteoclasts. According to the present invention, a peptide for inhibiting bone resorption can inhibit bone destruction by inhibiting the differentiation and activity of osteoclasts, and thus can be used as a therapeutic agent for various bone diseases caused by an excessive increase in the activity of osteoclasts.

Abstract: A capacitive fingerprint recognition unit using a thin-film transistor (TFT) sensor array to sense a user's fingerprint in a capacitive manner, a capacitance measurement circuit of a fingerprint sensor, and a fingerprint recognition device having the capacitance measurement circuit are disclosed. A capacitive fingerprint recognition unit includes a thin-film transistor (TFT) sensor array, a gate driver, an upper switch and a lower switch. The TFT sensor array includes a plurality of gate lines, a plurality of sensing lines, a plurality of TFTs connected to the gate line and the sensing line, and a fingerprint recognition pattern connected to each of the TFTs. The gate driver sequentially supplies a gate signal to the gate line. The upper switch is connected to a first end of each of the sensing lines and the lower switch is connected to a second end of each of the sensing lines.

Abstract: Provided herein is a memory controller and a method of operating the same. The memory controller may include a program erase counter configured to count a number of program and erase operations performed on the memory device and then generate a current program/erase count value, an error correction counter configured to count a number of error corrections for correcting error in an operation performed on the memory device and then generate a current error correction count value and a power consumption predictor configured to, predict a future program/erase count value based on the current program/erase count value, predict future power consumption of a storage device including the memory device and the memory controller, the future power consumption corresponding to the predicted program/erase count value and output information about the predicted power consumption to a host.

Abstract: A fingerprint sensor module and a fingerprint recognition device having the fingerprint sensor module are disclosed. A fingerprint sensor module includes a base film, a thin-film transistor sensor array, and a plurality of first signal lines, an external component and a plurality of second signal lines. The base film includes a fingerprint sensing area, a wing area surrounding the fingerprint sensing area, a first signal connecting area adjacent to the fingerprint sensing area, a component mounting area adjacent to the first signal connecting area, and a second signal connecting area adjacent to the component mounting area. The TFT sensor array is formed in the fingerprint sensing area. The first signal lines are formed in the first signal connecting area. The second signal lines are formed in the second signal connecting area.

Abstract: A method and apparatus for image conversion according to an embodiment of the present disclosure includes receiving original image data, separating the original image data into a front view image and a back view image for performing 3D conversion processing of the original image data, and generating a converted 3D image by restoring a background space between the front view image and the back view image using a 3D conversion processing neural network. The 3D conversion processing neural network according to the present disclosure may be a deep neural network generated by machine learning, and input and output of images may be performed in an Internet of things environment using a 5G network.

Abstract: In a method of preparing a lithium metal oxide, a preliminary lithium metal oxide is prepared. The preliminary lithium metal oxide is washed using a washing solution to remove lithium salt impurities. The washing solution includes water and an organic ligand multimer compound. The lithium metal oxide having improved structural uniformity and stability is obtained using the washing solution.

Abstract: A method and apparatus for image conversion according to an embodiment of the present disclosure includes receiving original image data, separating the original image data into a front view image and a back view image for performing 3D conversion processing of the original image data, and generating a converted 3D image by restoring a background space between the front view image and the back view image using a 3D conversion processing neural network. The 3D conversion processing neural network according to the present disclosure may be a deep neural network generated by machine learning, and input and output of images may be performed in an Internet of things environment using a 5G network.