Abstract: In generating a mask signal to be used when a clock signal embedded in an interface signal is recovered, when a mask rising signal for generating the mask signal is located in a data signal interval and a data signal indicates a high level, the mask signal may be generated in accordance with a falling edge of the data signal other than the mask rising signal.

Abstract: The present disclosure provides a technology indicating information different from each other by patterns of link data in a process of training links performed prior to transmitting image data.

Abstract: Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.

Abstract: Disclosed is a display device. The display device may use one transmission line to perform bidirectional data transmission between a timing controller and a source driver. Furthermore, the display device may control the timing controller to transmit a Tx signal to the source driver and control the source driver to transmit correction data, through one transmission line.

Abstract: The present disclosure provides a technology indicating information different from each other by patterns of link data in a process of training links performed prior to transmitting image data.

Abstract: An embodiment provides a display panel drive device that receives image data in a plurality of image reception periods within one frame period and retrains a data link according to link data received in an interval between the image reception periods.

Abstract: Provided are a data communication system for a high speed interface and a data transmission apparatus and a data reception apparatus of the data communication system. The data communication system includes the data transmission apparatus that configures a packet including a command and a plurality of components, determines a run length of data of the packet, and performs encoding, and the data reception apparatus that decodes the data of the encoded packet.

Abstract: Disclosed is an apparatus and method for transmitting a display signal having a protocol including a dummy signal and a clock signal. The apparatus for transmitting a display signal may include: a transmitter configured to transmit a display signal in which a dummy signal and a clock signal are sequentially embedded between image data; and a receiver configured to receive the display signal. Since a sufficient margin can be secured before and after the point of time that the clock signal is extracted between the image data, a stable operation of the system can be guaranteed, and the system interface can prevent the occurrence of EMI.

Abstract: Disclosed is a display driving device capable of reducing an output response delay of an output buffer. The display driving device may include: a first DAC configured to load a first grayscale voltage corresponding to first digital data as a first DAC signal; a second DAC configured to load a second grayscale voltage corresponding to second digital data as a second DAC signal; and an output buffer configured to alternately select the first DAC signal loaded to a first input terminal and the second DAC signal loaded to a second input terminal.

Abstract: Disclosed is a source driver for a display apparatus which is insensitive to power noise, and a configuration of filtering an influence of power noise, which is introduced from an exterior of the source driver or occurs in an interior thereof, to an operation of the source driver. The present invention is applied to the case of receiving a clock signal and a data signal through the single signal line, and is embodied such that a source driver for driving a display apparatus for achieving a high speed operation and a large screen has a characteristic insensitive to power noise.

Abstract: A display driving device may include: a source driving channel configured to provide a source driving signal corresponding to image data; a precharge unit configured to precharge a data output line of the source driving channel by selecting one of precharge voltages; and a precharge controller configured to decide whether to perform a precharge operation on the source driving channel depending on a variation of the image data, and control the precharge unit to select one of the precharge voltages when the performance of the precharge operation is decided.

Abstract: Disclosed is a display driving device. The display driving device may include: a buffer circuit including a positive output amplifier and a negative output amplifier; a switch circuit including output switches connected in series between the positive output amplifier and a first source output terminal, between the positive output amplifier and a second source output terminal, between the negative output amplifier and the first source output terminal, and between the negative output amplifier and the second source output terminal, respectively; and a reset circuit configured to reset output terminals of the positive output amplifier and the negative output amplifier to a middle voltage immediately before switching of the switch circuit for polarity inversion of the first and second source output terminals.

Abstract: Disclosed is a display driving device including a bonding resistance measurement circuit. The display driving device may include: first and second pads bonded to a pad of a display panel through a wire and configured to provide bonding resistance; and a bonding resistance measurement circuit configured to measure the bonding resistance by comparing an input voltage applied to the bonding resistance through the first pad to one or more preset reference voltages.

Abstract: An output circuit of a display driving device may include: a first buffer including first and third output units driven in a range of a positive output signal included in an output voltage domain corresponding to a display panel; a second buffer including second and fourth output units driven in a range of a negative output signal included in the output voltage domain corresponding to the display panel; a first body control unit configured to control a body voltage of the first output unit and the second output unit; and a second body control unit configured to control a body voltage of the third output unit and the fourth output unit.

Abstract: A source driver may include: a transmission line configured to transmit an output signal of a sample and hold circuit which stores pixel information of an organic light emitting diode (OLED) cell; an amplifier is formed a first offset voltage at an input terminal by a parasitic capacitor of the transmission line; and an offset voltage storage unit configured to store the first offset voltage outputted from the amplifier as a second offset voltage while the transmission of the output signal of the sample and hold circuit through the transmission line is turned off, and offset the first offset voltage by providing the second offset voltage to the input terminal of the amplifier when the output signal of the sample and hold circuit is transmitted through the transmission line.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: Disclosed is an apparatus and method for transmitting a display signal having a protocol including a dummy signal and a clock signal. The apparatus for transmitting a display signal may include: a transmitter configured to transmit a display signal in which a dummy signal and a clock signal are sequentially embedded between image data; and a receiver configured to receive the display signal. Since a sufficient margin can be secured before and after the point of time that the clock signal is extracted between the image data, a stable operation of the system can be guaranteed, and the system interface can prevent the occurrence of EMI.

Abstract: A sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

Abstract: Disclosed is a display device. The display device may use one transmission line to perform bidirectional data transmission between a timing controller and a source driver. Furthermore, the display device may control the timing controller to transmit a Tx signal to the source driver and control the source driver to transmit correction data, through one transmission line.

Abstract: A display driving circuit may include: an output buffer unit including a plurality of output buffer pairs, wherein among the plurality of output buffer pairs, each of first output buffers has a first voltage driving potential, and each of second output buffers has a second voltage driving potential; an output switch unit configured to directly connect the plurality of output buffer pairs to a plurality of output line pairs or cross and connect the plurality of output buffer pairs to the plurality of output line pairs; and a charge sharing switch unit configured to connect first output lines corresponding to the first output buffers, and connect second output lines corresponding to the second output buffers. Through this configuration, the display driving circuit can reduce power consumption and heat generation.