Abstract: A power noise prevention circuit in an MCU, includes a system clock generating circuit generating a system clock signal by receiving a clock signal, a clock freezing and synchronizing part outputting the system clock signal during a power failure, a reset circuit resetting an MCU during the power failure, a power fail detection circuit detecting a power level based on a freeze level and a reset level, and a power fail detection register controlling a detection operation and a detection mode of the power fail detection circuit. The power fail detection circuit operates the clock freezing and synchronizing part when a power level reaches the freeze level, and operates the reset circuit when the power level reaches the reset level.

Abstract: The present invention relates to a circuit that prevents or reduces power consumption in a dynamic logic circuit. The circuit according to the present invention that inhibits power consumption effectively reduces subthreshold leakage current particularly when generated in a standby state of the dynamic logic. The present invention can include a dynamic logic provided with first and second MOS transistors of a conductive type different from each other and a power selection unit. The power selection unit outputs first and second voltages different from each other according to an output level of the dynamic logic. The power selection unit outputs a power voltage and a substrate voltage as first and second voltages when the output of the dynamic logic is at a high level, or outputs a boosting voltage and a ground voltage as the first and second voltages when the output of the dynamic logic is at a high level.

Abstract: A power noise prevention circuit in an MCU, includes a system clock generating circuit generating a system clock signal by receiving a clock signal, a clock freezing and synchronizing part outputting the system clock signal during a power failure, a reset circuit resetting an MCU during the power failure, a power fail detection circuit detecting a power level based on a freeze level and a reset level, and a power fail detection register controlling a detection operation and a detection mode of the power fail detection circuit. The power fail detection circuit operates the clock freezing and synchronizing part when a power level reaches the freeze level, and operates the reset circuit when the power level reaches the reset level.

Abstract: The present invention relates to a circuit that prevents or reduces power consumption in a dynamic logic circuit. The circuit according to the present invention that inhibits power consumption effectively reduces subthreshold leakage current particularly when generated in a standby state of the dynamic logic. The present invention can include a dynamic logic provided with first and second MOS transistors of a conductive type different from each other and a power selection unit. The power selection unit outputs first and second voltages different from each other according to an output level of the dynamic logic. The power selection unit outputs a power voltage and a substrate voltage as first and second voltages when the output of the dynamic logic is at a high level, or outputs a boosting voltage and a ground voltage as the first and second voltages when the output of the dynamic logic is at a high level.