Abstract: Provided are an output buffer circuit capable of outputting a pair of output signals having different polarities and a display driving circuit including the same. The output buffer circuit includes output buffers which output a positive output signal and a negative output signal in response to a pair of input signals having different polarities. As the output buffers are driven while sharing a common voltage, the output buffer circuit satisfies a low-power specification, and has a stable electrical characteristic.

Abstract: A sample and hold circuit may include: a main sample and hold circuit configured to sample and hold pixel information of an organic light emitting diode (OLED) cell, and output a first output signal; and a dummy sample and hold circuit configured to sample and hold a reference voltage in synchronization with the main sample and hold circuit, and output a second output signal for offsetting a switching noise signal contained in the first output signal.

Abstract: A source driver may include: a transmission line configured to transmit an output signal of a sample and hold circuit which stores pixel information of an organic light emitting diode (OLED) cell; an amplifier is formed a first offset voltage at an input terminal by a parasitic capacitor of the transmission line; and an offset voltage storage unit configured to store the first offset voltage outputted from the amplifier as a second offset voltage while the transmission of the output signal of the sample and hold circuit through the transmission line is turned off, and offset the first offset voltage by providing the second offset voltage to the input terminal of the amplifier when the output signal of the sample and hold circuit is transmitted through the transmission line.

Abstract: The present invention relates to a source driver of a display apparatus, and relates to a source driver for display apparatus insensitive to power noise, which forcibly decides an internal operation state as normality in a specific period including a power noise generation period and operates insensitively to the power noise. Accordingly, the display apparatus can normally output an image voltage even though power noise occurs.

Abstract: A display driving system includes a timing control section having an LVDS receiving unit for receiving data signals, a data processing unit for temporarily storing the data signals, processing the data signals and outputting processed data signals, a timing generation unit for generating clock signals and timing control signals, and a transmission unit for transmitting the data signals; and a panel driving section having row driving units for sequentially emitting gate signals toward a display panel and column driving units for receiving the signals transmitted through signal lines from the transmission unit and supplying the received signals to the display panel. In the timing control section, the transmission unit has driving parts which embed the clock signals between the data signals at the same level and generate and output single level transmission data.

Abstract: Disclosed are a display driving circuit and a display device. The display driving circuit includes an output buffer unit that outputs a pair of pixel signals, an output switch unit that directly transfers the pair of pixel signals to a pair of output lines or transfers the pair of pixel signals to the pair of output lines such that the pair of pixel signals cross each other in correspondence with repetitive panel charging/discharging periods, and a charge sharing switch unit that controls charge sharing of the pair of output lines in correspondence with a charge sharing period between the panel charging/discharging periods, and provides a variable connection resistance value for the charge sharing. Consequently, power consumption and heat generation of the display driving circuit are reduced.

Abstract: Disclosed is a display driving circuit including an output buffer unit that is connected to a common voltage and first and second voltages and outputs a pair of pixel signals; an output switch that directly connects the pair of pixel signals to a pair of output lines or connects the pair of pixel signals to the pair of output lines such that they cross each other; and a pre-charging unit that charges the pair of output lines by using pre-charging voltages. Consequently, power consumption and heat generation of the display driving circuit are reduced.

Abstract: A display driving system using single level data transmission with embedded clock signals. The display driving system is configured to embed a clock signal of the same level between data signals and transmit these signals as a single level signal, wherein a cycle at which clock signals are embedded is controlled and a data format is constructed such that a control data transmission step can be extended over 2 words.

Abstract: Disclosed is a source driver for a display apparatus which is insensitive to power noise, and a configuration of filtering an influence of power noise, which is introduced from an exterior of the source driver or occurs in an interior thereof, to an operation of the source driver. The present invention is applied to the case of receiving a clock signal and a data signal through the single signal line, and is embodied such that a source driver for driving a display apparatus for achieving a high speed operation and a large screen has a characteristic insensitive to power noise.

Abstract: Embodiments of the present invention provide a method and apparatus for transmitting data between a timing controller and a source driver. In some embodiments, the method includes a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.

Abstract: A display driving system includes a timing controller configured to receive a data signal composed of image data and generate a control signal such as a clock signal; an interface configured to transmit the data signal and the control signal to a plurality of data drivers; the data drivers configured to receive the data signal and the control signal through the interface and supply received signals to a display panel to display an image; and a monitoring unit configured to feed back LOCK signals indicative of state information of the data drivers to the timing controller such that the data drivers can be monitored.

Abstract: The present invention relates to three-branched PEG-G-CSF conjugate of general formula (1) in which the bonding ratio of three-branched polyethylene glycol (PEG) and G-CSF is 1:1 (mol/mol), wherein PEG has an average molecular weight of from 200 to 45,000 daltons; a pharmaceutical composition comprising the same, and a preparing method thereof.

Abstract: Disclosed is a method and apparatus for transmitting data between a timing controller and a source driver, and more particularly, a data transmission method and apparatus between a timing controller and a source driver, which has a bit error rate test (BERT) function for sensing an error rate in real time when data is transmitted and received between the timing controller and the source driver.

Abstract: A receiver for receiving an input signal (a clock-embedded data (CED) signal), in which a clock signal is periodically embedded between data signals, includes a clock recovery unit configured to recover and output the clock signal and a serial-to-parallel converter configured to recover and output a data signal. The input signal (the CED signal) comprises a single level signal in which the clock signal is periodically embedded between the data signals at the same level. The clock recovery unit is configured based on a delay locked loop (DLL) without using an internal oscillator for generating a reference clock signal.

Abstract: A display driving system using single level data transmission with embedded clock signals. The display driving system is configured to embed a clock signal of the same level between data signals and transmit these signals as a single level signal, wherein a cycle at which clock signals are embedded is controlled and a data format is constructed such that a control data transmission step can be extended over 2 words.

Abstract: A display driving system includes a timing control section having an LVDS receiving unit for receiving data signals, a data processing unit for temporarily storing the data signals, processing the data signals and outputting processed data signals, a timing generation unit for generating clock signals and timing control signals, and a transmission unit for transmitting the data signals; and a panel driving section having row driving units for sequentially emitting gate signals toward a display panel and column driving units for receiving the signals transmitted through signal lines from the transmission unit and supplying the received signals to the display panel. In the timing control section, the transmission unit has driving parts which embed the clock signals between the data signals at the same level and generate and output single level transmission data.

Abstract: A display driving system includes a timing controller configured to receive a data signal composed of image data and generate a control signal such as a clock signal; an interface configured to transmit the data signal and the control signal to a plurality of data drivers; the data drivers configured to receive the data signal and the control signal through the interface and supply received signals to a display panel to display an image; and a monitoring unit configured to feed back LOCK signals indicative of state information of the data drivers to the timing controller such that the data drivers can be monitored.

Abstract: The present invention relates to three-branched PEG-G-CSF conjugate of general formula (1) in which the bonding ratio of three-branched polyethylene glycol (PEG) and G-CSF is 1:1 (mol/mol), wherein PEG has an average molecular weight of from 200 to 45,000 daltons; a pharmaceutical composition comprising the same, and a preparing method thereof.

Abstract: The present invention relates to three-branched polyethylene glycol-interferon alpha conjugate of general formula (1) wherein polyethylene glycol has an average molecular weight of from 400 to 45,000 daltons, and a pharmaceutical composition comprising the same. The bioactive polyethylene glycol-interferon alpha conjugate of general formula (1) has antiviral and antitumoral activities, improved yield and purity by high reactivity in the reaction, and the effects to increase the half-life in blood remarkably, and to minimize the decreases in biological activity of interferon.