Patents by Inventor Hyun Min Choi

Hyun Min Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170154890
    Abstract: A one time programmable (OTP) memory device, a method of manufacturing the same, and an electronic device including the same, which lower a programming voltage to enhance programming efficiency, increase reliability of peripheral input/output (I/O) elements used for a design of the OTP memory device, and simplify the design, are provided. The OTP memory device includes a transistor including one of a first gate structure including a high-k dielectric layer, a rare earth element (RE) supply layer, and a second metal layer, a second gate structure including the high-k dielectric layer, a first metal layer, and the second metal layer, and a third gate structure including the high-k dielectric layer and the second metal layer.
    Type: Application
    Filed: November 9, 2016
    Publication date: June 1, 2017
    Inventors: Min-jung Jin, Sang-woo Pae, Hyun-min Choi
  • Publication number: 20170155756
    Abstract: A method, device, a non-transitory computer-readable recording medium for controlling a voice signal by an electronic device including a first microphone, a second microphone, a communication interface, and a processor are provided. The method includes acquiring a first voice signal by using the first microphone; acquiring a second voice signal by using the second microphone; confirming a telephone call mode for performing, by the electronic device, a telephone call with an external electronic device; adjusting a first output attribute corresponding to the first voice signal or a second output attribute corresponding to the second voice signal, based on the telephone call mode; and transmitting the adjusted first voice signal or the adjusted second voice signal to the external electronic device by using the communication interface.
    Type: Application
    Filed: November 28, 2016
    Publication date: June 1, 2017
    Inventors: Gang-Youl KIM, Jun-Tai KIM, Min-Ho BAE, Beak-Kwon SON, Jung-Yeol AN, Chui-Min CHOI, Yang-Su KIM, Jae-Mo YANG, Nam-Woog LEE, Keun-Won JANG, Hyun-Min CHOI
  • Patent number: 9666526
    Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: May 30, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-Min Choi
  • Patent number: 9646711
    Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end; a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the firs
    Type: Grant
    Filed: April 2, 2015
    Date of Patent: May 9, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Patent number: 9627314
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Grant
    Filed: January 4, 2016
    Date of Patent: April 18, 2017
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Patent number: 9627390
    Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.
    Type: Grant
    Filed: April 10, 2015
    Date of Patent: April 18, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda, Ji-Hoon Yoon
  • Publication number: 20170069570
    Abstract: In a semiconductor device and a method of manufacturing the same a fuse structure may be formed during formation of first to third contact plugs connected to a transistor. The fuse structure may include first and second fuse contact plugs having the same height as the first and second contact plugs, and a connection pattern having the same height as the third contact plug. The connection pattern may be connected between the first and second fuse contact plugs.
    Type: Application
    Filed: August 5, 2016
    Publication date: March 9, 2017
    Inventors: Jihoon Yoon, Shincheol Min, Hyun-Min Choi
  • Publication number: 20170055072
    Abstract: An electronic device is provided. The electronic includes a camera module and a processor configured to capture at least one image of an object using the camera module, obtain a sound using a microphone operably connected to the processor when the at least one image is captured, determine whether the sound is related to the object, when the sound is determined to be unrelated to the object, change at least one attribute of the sound and store the changed at least one attribute of the sound.
    Type: Application
    Filed: June 20, 2016
    Publication date: February 23, 2017
    Inventors: Jun-Tai KIM, Min-Ho Bae, Hyun-Min Choi, Han-Ho Ko, Gang-Youl Kim, Jae-Mo Yang, Chul-Min Choi, Beak-Kwon Son, Nam-II Lee
  • Publication number: 20170047335
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.
    Type: Application
    Filed: October 26, 2016
    Publication date: February 16, 2017
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Jihoon YOON, SUNGMAN LIM
  • Publication number: 20170047287
    Abstract: An eFuse structure of a semiconductor device may include a first metal formed at a first level on a substrate, a second metal formed at a second level between the first level and the substrate, a third metal formed at a third level between the second level and the substrate, a first via connecting the first metal to the second metal, and a second via connecting the second metal to the third metal. The first metal may include a first portion extending in a first direction, a second portion extending in the first direction and being adjacent to the first portion, and a third portion connecting the first portion to the second portion. A first distance between the first portion and the second portion may be greater than a width of the second portion in a second direction perpendicular to the first direction.
    Type: Application
    Filed: August 4, 2016
    Publication date: February 16, 2017
    Inventor: Hyun-Min CHOI
  • Patent number: 9540549
    Abstract: A semiconductor device bonded by an anisotropic conductive film and an anisotropic conductive film composition, the anisotropic conductive film including a reactive monomer having an epoxy equivalent weight of about 120 to about 180 g/eq; a hydrogenated epoxy resin; and a sulfonium cation curing catalyst.
    Type: Grant
    Filed: December 18, 2012
    Date of Patent: January 10, 2017
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Kyung Il Sul, Dong Seon Uh, Nam Ju Kim, Kyoung Soo Park, Young Woo Park, Joon Mo Seo, Arum Yu, Hyun Min Choi
  • Patent number: 9502425
    Abstract: The inventive concepts provide semiconductor devices and methods of manufacturing the same. One semiconductor device includes a substrate, a device isolation layer disposed on the substrate, a fin-type active pattern defined by the device isolation layer and having a top surface higher than a top surface of the device isolation layer, a first conductive line disposed on an edge portion of the fin-type active pattern and on the device isolation layer adjacent to the edge portion of the fin-type active pattern, and an insulating thin layer disposed between the fin-type active pattern and the first conductive line. The first conductive line forms a gate electrode of an anti-fuse that may be applied with a write voltage.
    Type: Grant
    Filed: November 4, 2014
    Date of Patent: November 22, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda, Jihoon Yoon, Sungman Lim
  • Patent number: 9419004
    Abstract: A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device.
    Type: Grant
    Filed: December 18, 2014
    Date of Patent: August 16, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Patent number: 9397234
    Abstract: A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region.
    Type: Grant
    Filed: April 24, 2015
    Date of Patent: July 19, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-min Choi, Ju-youn Kim, Hyun-jo Kim, Mu-kyeng Jung
  • Patent number: 9390831
    Abstract: An electronic device includes a connection material formed from an adhesive composition that includes: a polymer resin; a cationic polymerization catalyst represented by Formula 1; and an organic base, where, in Formula 1, R1 may be selected from the group of hydrogen, C1-C6 alkyl, C6-C14 aryl, —C(?O)R4, —C(?O)OR5, and —C(?O)NHR6 (in which R4, R5, and R6 may each independently be selected from C1-C6 alkyl and C6-C14 aryl), R2 may be C1-C6 alkyl, and R3 may be selected from the group of a nitrobenzyl group, a dinitrobenzyl group, a trinitrobenzyl group, a benzyl group, a C1-C6 alkyl-substituted benzyl group, and a naphthylmethyl group.
    Type: Grant
    Filed: November 19, 2012
    Date of Patent: July 12, 2016
    Assignee: CHEIL INDUSTRIES INC.
    Inventors: Kyoung Soo Park, Nam Ju Kim, Young Woo Park, Joon Mo Seo, Kyung Il Sul, Dong Seon Uh, Arum Yu, Hyun Min Choi, Jae Sun Han
  • Patent number: 9390812
    Abstract: An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: July 12, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, In-Gyu Park, Jung-Hak Song
  • Patent number: 9368445
    Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: June 14, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Publication number: 20160163643
    Abstract: E-fuse devices, and a method of manufacturing the same, include a first metal pattern extending in a first direction to connect a first electrode and a second electrode to each other, a first barrier metal contacting lateral surfaces and a bottom surface of the first metal pattern, and a first capping insulation layer contacting a top surface of the first metal pattern, wherein the first metal pattern includes an exposed region, the first barrier metal or the first capping insulation layer not contacting a top surface or a bottom surface of the exposed region.
    Type: Application
    Filed: December 1, 2015
    Publication date: June 9, 2016
    Inventors: Hyun-Min CHOI, Chul-Yong Park
  • Patent number: 9336894
    Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
    Type: Grant
    Filed: June 29, 2015
    Date of Patent: May 10, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda, Ji-Hoon Yoon
  • Patent number: 9331085
    Abstract: A semiconductor device may include: a substrate. First and second gate electrode patterns are disposed on first and second fin type active patterns. The first and second fin type active patterns include a first channel region disposed between a first impurity region and a second impurity region. The second gate electrode pattern crosses a first gate-separating region included in the second fin type active region. The first gate-separating region includes a trench and an embedded insulator filling at least a portion of the trench.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 3, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun Min Choi, Shin Cheol Min, Ji Hoon Yoon