Patents by Inventor Hyun Min Choi

Hyun Min Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160118342
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Application
    Filed: January 4, 2016
    Publication date: April 28, 2016
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Publication number: 20160093621
    Abstract: A memory device including one-time programmable memory cells has a semiconductor substrate with a write region and a read region, a write gate provided on the write region, a read gate provided on the read region, first and second junction patterns provided at both sides of the read gate, and insulating dielectric patterns interposed between the write and read gates and the semiconductor substrate. The read region may have a different conductivity type from the first and second junction patterns, and the write region may have the same conductivity type as the first and second junction patterns.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 31, 2016
    Inventors: Hyun-Min Choi, Sangwoo Pae, Hagju Cho
  • Publication number: 20160093398
    Abstract: A memory device may include nonvolatile memory cells. A first memory cell of the nonvolatile memory cells may have a first resistance value in a first state and a second memory cell of the nonvolatile memory cells may have a second resistance value less than the first resistance value in a second state. A third memory cell of the nonvolatile memory cells may have a third resistance value less than the first resistance value and greater than the second resistance value in a third state, and a fourth memory cell of the nonvolatile memory cells may have a fourth resistance value less than the third resistance value and greater than the second resistance value in a fourth state.
    Type: Application
    Filed: June 29, 2015
    Publication date: March 31, 2016
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Ji-Hoon YOON
  • Patent number: 9293701
    Abstract: A variable resistance memory device includes a gate pattern and a dummy gate pattern provided at the same level on a substrate, a first contact pattern provided on the dummy gate pattern, and a variable resistance pattern provided between the dummy gate pattern and the first contact pattern. The gate pattern and the dummy gate pattern define conductive electrodes of functional and non-functional transistors, respectively. The first contact pattern and the dummy gate pattern define upper and lower electrodes on the variable resistance pattern, respectively. Related fabrication methods are also discussed.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: March 22, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Juyoun Kim, Shigenobu Maeda, Jihoon Yoon, Sungman Lim
  • Publication number: 20160079446
    Abstract: A pumping capacitor is provided. The pumping capacitor includes a substrate, a P-type gate layer on the substrate, and a gate dielectric layer between the substrate and the P-type gate layer. The substrate includes an N-type well region and an N-type doping region in the N-type well region.
    Type: Application
    Filed: April 24, 2015
    Publication date: March 17, 2016
    Inventors: Hyun-min CHOI, Ju-youn KIM, Hyun-jo KIM, Mu-kyeng JUNG
  • Publication number: 20160064390
    Abstract: A semiconductor device may include: a substrate. First and second gate electrode patterns are disposed on first and second fin type active patterns. The first and second fin type active patterns include a first channel region disposed between a first impurity region and a second impurity region. The second gate electrode pattern crosses a first gate-separating region included in the second fin type active region. The first gate-separating region includes a trench and an embedded insulator filling at least a portion of the trench.
    Type: Application
    Filed: April 7, 2015
    Publication date: March 3, 2016
    Inventors: Hyun Min Choi, Shin Cheol Min, Ji Hoon Yoon
  • Publication number: 20160056109
    Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.
    Type: Application
    Filed: November 5, 2015
    Publication date: February 25, 2016
    Inventor: Hyun-Min CHOI
  • Publication number: 20160005494
    Abstract: An e-fuse test device is provided. The e-fuse test device may include a first transistor, and a fuse array connected to a source/drain terminal of the first transistor. The fuse array may include n fuse groups, each of the fuse groups may include one end, the other end, and m first fuse elements connected in series to each other between the one end and the other end, the one end of each of the fuse groups may be connected to each other, and the other end of each of the fuse groups may be connected to the source/drain terminal of the first transistor, and the n and m are natural numbers that are equal to or larger than two.
    Type: Application
    Filed: May 15, 2015
    Publication date: January 7, 2016
    Inventors: Hyun-Min CHOI, In-Gyu PARK, Jung-Hak SONG
  • Patent number: 9230925
    Abstract: A fuse structure and a method of blowing the same are provided. The fuse structure includes a conductive line on a substrate, first and second vias on the conductive line that are spaced apart from each other, a cathode electrode line that is electrically connected to the first via, an anode electrode line that is electrically connected to the second via, and a dummy pattern that is adjacent at least one of the cathode and anode electrode lines and electrically isolated from the conductive line.
    Type: Grant
    Filed: April 25, 2014
    Date of Patent: January 5, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Publication number: 20150380102
    Abstract: A memory device includes first through fourth active regions arranged sequentially along a first direction, and which extend along a second direction different from the first direction; a first gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, and extending along the first direction; a second gate electrode formed on the first through fourth active regions to intersect the first through fourth active regions, extending along the second direction, and arranged so that no other gate electrodes are between the first gate electrode and the second gate electrode in the second direction; the first gate electrode extending between a first end and a second end; a first wiring line which is formed on the first gate electrode; a first strap contact, which connects the first wiring line and the first gate electrode between the first active region and the second active region; and a second strap contact, which connects the first wiring line and the firs
    Type: Application
    Filed: April 2, 2015
    Publication date: December 31, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Patent number: 9214245
    Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.
    Type: Grant
    Filed: December 3, 2014
    Date of Patent: December 15, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventor: Hyun-Min Choi
  • Publication number: 20150340317
    Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 26, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA
  • Patent number: 9173303
    Abstract: An apparatus includes a first member including a plurality of first electrodes on a first substrate, a second member including a plurality of second electrodes on a second substrate, the second electrodes facing the first electrodes of the first member, and an anisotropic conductive film (ACF) between the first member and the second member, the ACF having a double-layered structure and electrically connecting the first member and the second member, the ACF including an epoxy resin with a polycyclic aromatic ring and exhibiting a minimum melt viscosity of about 3,000 Pa·s to about 10,000 Pa·s at about 30° C. to about 200° C.
    Type: Grant
    Filed: December 6, 2011
    Date of Patent: October 27, 2015
    Assignee: CHEIL INDUSTRIES, INC.
    Inventors: Young Woo Park, Arum Amy Yu, Nam Ju Kim, Hyun Min Choi, Jin Seong Park, Dong Seon Uh
  • Publication number: 20150294979
    Abstract: A semiconductor device is provided. The semiconductor device includes: a plurality of fin-type active patterns which extend along a first direction, and are arranged with respect to each other along a second direction different from the first direction; a contact which is electrically connected to the plurality of fin-type active patterns; a first gate electrode which extends along the second direction and is formed on at least two of the plurality of fin-type active patterns; and a second gate electrode which extends along the second direction and is formed on at least one of the plurality of fin-type active patterns. The first gate electrode is disposed between the contact and the second gate electrode, and the number of fin-type active patterns intersected by the first gate electrode is greater than the number of fin-type active patterns intersected by the second gate electrode.
    Type: Application
    Filed: April 10, 2015
    Publication date: October 15, 2015
    Inventors: Hyun-Min CHOI, Shigenobu MAEDA, Ji-Hoon YOON
  • Publication number: 20150255469
    Abstract: A fuse structure includes a first fin pattern disposed in a field insulating layer that includes an upper surface that projects above an upper surface of the field insulating layer, a conductive pattern on the field insulating layer that crosses the first fin pattern, a first semiconductor region positioned on at least one side of the conductive pattern, and first and second contacts disposed on the conductive pattern on each side of the first fin pattern. The fuse structure may be included in a semiconductor device.
    Type: Application
    Filed: December 18, 2014
    Publication date: September 10, 2015
    Inventors: HYUN-MIN CHOI, Shigenobu Maeda
  • Patent number: 9099469
    Abstract: Provided is an e-fuse structure of a semiconductor device. the e-fuse structure may include a fuse link formed of a first metal material to connect a cathode with an anode, a capping dielectric covering a top surface of the fuse link, and a dummy metal plug penetrating the capping dielectric and being in contact with a portion of the fuse link. The dummy metal plug may include a metal layer and a barrier metal layer interposed between the metal layer and the fuse link. The barrier metal layer may be formed of a second metal material different from the first metal material.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: August 4, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda
  • Publication number: 20150206603
    Abstract: Provided is an e-fuse structure of a semiconductor device having improved fusing performance so as to enable a program operation at a low voltage. The e-fuse structure includes a first metal pattern formed at a first vertical level, the first metal pattern including a first part extending in a first direction and a second part extending in the first direction and positioned to be adjacent to the first part, and a third part adjacent to the second part, the second part being positioned between the first part and the third part, the first part and the second part being electrically connected to each other, and the third part being electrically disconnected from the second part; and a second metal pattern electrically connected to the first metal pattern and formed at a second vertical level different from the first vertical level.
    Type: Application
    Filed: December 3, 2014
    Publication date: July 23, 2015
    Inventor: Hyun-Min CHOI
  • Patent number: 9087803
    Abstract: Methods of fabricating integrated circuit devices utilize fuse elements to support sequential testing of vertically-integrated test elements during fabrication. These methods include forming a first test element, a first fuse and a first test pad electrically connected by the first fuse to the first test element, on a substrate. The first test element is tested by passing a first current between the first test element and first test pad and through the first fuse. The first fuse is then “cut” by increasing an impedance of the first fuse, which may include breaking the first fuse to create an electrical “open” (infinite impedance) or greatly increasing a resistance of the first fuse (e.g., by narrowing the fuse through electromigration). A second test element and a second test pad, which is electrically connected to the second test element and the first test pad, are then formed on the substrate.
    Type: Grant
    Filed: November 18, 2011
    Date of Patent: July 21, 2015
    Assignees: Samsung Electronics Co., Ltd., International Business Machines Corporation
    Inventors: Jeong-Hoon Ahn, Hyun-Min Choi, Oluwafemi O. Ogunsola
  • Patent number: 9087842
    Abstract: A semiconductor device includes a substrate having a fuse area and a device area; a fuse structure in an insulating layer of the fuse area, and a wire structure in the insulating layer of the device area. The fuse structure includes a fuse via, a fuse line electrically connected to a top end of the fuse via pattern and extending in a direction. The wire structure includes a wire via, a wire line electrically connected to a top end of the wire via and extending in the first direction. A width in the first direction of the fuse via is smaller than a width in the first direction of the wire via.
    Type: Grant
    Filed: June 13, 2014
    Date of Patent: July 21, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyun-Min Choi, Shigenobu Maeda, Ji-Hoon Yoon, Sung-Man Lim
  • Patent number: 9059090
    Abstract: A method of fabricating a semiconductor device includes forming a first gate pattern and a dummy gate pattern on a first active area and a second active area of a substrate, respectively, the first gate pattern including a first gate insulating layer and a silicon gate electrode, removing the dummy gate pattern to expose a surface of the substrate in the second active area, forming a second gate pattern including a second gate insulating layer and a metal gate electrode on the exposed surface of the substrate, the first gate insulating layer having a thickness larger than a thickness of the second gate insulating layer, and forming a gate silicide on the silicon gate electrode after forming the second gate pattern.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: June 16, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ju-Youn Kim, Hyun-Min Choi, Sung-Kee Han, Je-Don Kim