Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

Abstract: A resistive memory device includes a stack of two layers of variable resistance material and top, middle, and bottom electrodes, the stack symmetrical in composition about the middle electrode.

Abstract: The present invention relates to a resistance change memory device and a method for manufacturing the same.

Abstract: The present invention relates to a pattern recognition method and a pattern recognition apparatus for the same. According to the present invention, a pattern recognition method comprises: receiving data of a recognition object having a pattern; and recognizing the pattern using an electronic device having a synapse characteristic including a plurality of RRAMs (Resistance Random Access Memories), wherein each RRAM includes a variable resistance layer and has multiple memory states depending on variations in resistance of the variable resistance layer.

Abstract: A three-terminal synapse device may include a drain layer formed on a substrate, a gate layer formed on the drain layer, a source layer vertically stacked on the substrate and facing the drain layer and the gate layer. First and second vertical insulating layers may be formed between the source layer and a stack including the drain layer and the gate layer. The first and second vertical insulating layers have different ion mobilities from each other. The first and second vertical insulating layers may cover side surfaces of the drain layer and the gate layer. The ion mobility of the second vertical insulating layer may be greater than that of the first vertical insulating layer.

Abstract: Hybrid resistive memory devices and methods of operating and manufacturing the same, include at least two resistive memory units. At least one of the at least two resistive memory units is a resistive memory unit configured to operate in a long-term plasticity state.

Abstract: Disclosed is a nonvolatile resistive random access memory. The nonvolatile resistive random access memory includes a first electrode, a second electrode, an ion conducting layer disposed between the first and second electrodes, a first heat diffusion preventing layer formed on the first electrode, and a second heat diffusion preventing layer formed on the second electrode. Since a temperature of a switching region of a device increases by adding the heat diffusion preventing layer, an operation speed increases by ten or more times, and a data retention of the device can be identically maintained. Accordingly, a voltage-time dilemma can be solved without an increase in an area of the device, thereby improving a degree of integration.

Abstract: Disclosed is a nonvolatile resistive random access memory. The nonvolatile resistive random access memory includes an upper electrode, a lower electrode, an ion supply layer formed on the lower electrode, and a resistance change layer formed on the ion supply layer. The ion supply layer includes copper-doped carbon. A low-power switching operation is performed because the optimal filament is formed by limiting the number of supplied ions, without using the existing method that supplies infinite ions by using a metal electrode.

Abstract: Hybrid resistive memory devices and methods of operating and manufacturing the same, include at least two resistive memory units. At least one of the at least two resistive memory units is a resistive memory unit configured to operate in a long-term plasticity state.

Abstract: A frequency tuning apparatus may include an oscillator and a memory element connected to the oscillator. The memory element may have a variable resistance. An oscillation frequency of the oscillator may vary according to a resistance state of the memory element. The oscillator may be a ring oscillator. The memory element may be connected to an input terminal or a power terminal of the oscillator.

Abstract: Provided are a resistance change memory device with a three-dimensional structure, a resistance change memory device array, an electronic product, and a manufacturing method therefor. The device array includes a plurality of first directional data lines which are arranged on a substrate in parallel. A conductive pillar is positioned between sidewalls of the first directional data lines, which face each other. A resistance change material film is positioned between the sidewall of the conductive pillar and the sidewall of the data lines that are adjacent to the sidewall of the conductive pillar.

Abstract: A switching device that provides bipolar current paths and a resistance change memory device using the switching device. The switching device includes a first electrode, a second electrode, and an amorphous carbon layer interposed between the first electrode and the second electrode and configured to control a bipolar current to flow therethrough in response to a voltage applied between the first electrode and the second electrode.

Abstract: A resistive random access memory (ReRAM) includes a first electrode, a threshold switching layer formed over the first electrode and configured to perform a switching operation according to an applied voltage, a resistance change layer formed over the threshold switching layer, and configured to perform a resistance change operation, and a second electrode formed over the resistance change layer, wherein the threshold switching layer comprises a stoichiometric transition oxide while the resistance change layer comprises a non-stoichiometric transition metal oxide.

Abstract: A resistance RAM includes a first electrode, an oxide layer that is formed on the first electrode, a solid electrolyte layer that is disposed on the oxide layer, and a second electrode that is disposed on the solid electrolyte layer. A method of forming the resistance RAM includes forming a conductive tip in the oxide layer by applying reference voltage to any one of the electrodes of the resistance RAM, and applying foaming voltage to the remaining one, such that the oxide layer is electrically broken. A conductive filament is formed in the solid electrolyte layer by applying a positive voltage to the second electrode, and the conductive filament that is formed in the solid electrolyte layer is removed by applying a negative voltage to the second electrode.

Abstract: Provided are a resistance change memory device with a three-dimensional structure, a resistance change memory device array, an electronic product, and a manufacturing method therefor. The device array includes a plurality of first directional data lines which are arranged on a substrate in parallel. A conductive pillar is positioned between sidewalls of the first directional data lines, which face each other. A resistance change material film is positioned between the sidewall of the conductive pillar and the sidewall of the data lines that are adjacent to the sidewall of the conductive pillar.

Abstract: Provided is a resistance random access memory (RRAM) device and a method of manufacturing the same. A resistance random access memory (RRAM) device may include a lower electrode, a first oxide layer on the lower electrode and storing information using two resistance states, a current control layer made of a second oxide on the first oxide layer and an upper electrode on the current control layer.

Abstract: Disclosed are a resistance-variable memory device including a carbide-based solid electrolyte membrane that has stable memory at a high temperature and a manufacturing method thereof. The resistance-variable memory device includes: a lower electrode, the carbide-based solid electrolyte membrane arranged on the lower electrode, and an upper electrode arranged on the solid electrolyte membrane. In addition, the method for manufacturing the resistance-variable memory device comprises: a step for forming the lower electrode on a substrate, a step for forming the carbide-based solid electrolyte membrane on the lower electrode, and a step for forming the upper electrode on the solid electrolyte membrane.

Abstract: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.

Abstract: A resistance RAM that is provided with an oxide layer and a solid electrolyte layer, and a method for operating the same are provided. The resistance RAM comprises a first electrode, an oxide layer that is formed on the first electrode, a solid electrolyte layer that is disposed on the oxide layer, and a second electrode that is disposed on the solid electrolyte layer. The method comprises the step of forming a conductive tip in the oxide layer by applying reference voltage to any one of the electrodes of the resistance RAM, applying foaming voltage to the remain one, such that the oxide layer is electrically broken. A conductive filament is formed in the solid electrolyte layer by applying a positive voltage to the second electrode on the basis of the voltage that is applied to the first electrode. The conductive filament that is formed in the solid electrolyte layer is removed by applying a negative voltage to the second electrode on the basis of the voltage that is applied to the first electrode.

Abstract: A semiconductor memory device includes a first dopant area and a second dopant area in a semiconductor substrate, the first dopant area and the second dopant area doped with one selected from the group consisting of Sb, Ga, and Bi. The semiconductor memory device includes an insulating layer disposed in contact with the first dopant area and the second dopant area, and a gate electrode layer disposed in contact with the insulating layer.