Abstract: A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of memory cells, a peripheral circuit for applying a program voltage and verifying whether a program of the memory cell array has been completed, and a control logic for controlling the peripheral circuit to apply an increased program voltage to the memory cell array while applying a reprogram permission voltage to a bit line coupled to the memory cells that previously passed a program verification but has failed a program re-verification.

Abstract: A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.

Abstract: A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell. The semiconductor memory device may include a voltage generator configured for generating a program voltage applied to a normal memory cell selected among the plurality of normal memory cells, and for generating a dummy word line voltage applied to the dummy memory cell in a program operation. The semiconductor memory device may include a control logic configured for controlling the voltage generator to adjust the dummy word line voltage based on the program voltage.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.

Abstract: A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A semiconductor memory and a method of programming the same are provided. A semiconductor memory device may include a memory cell array including a plurality of normal memory cells, a select transistor, and a dummy memory cell. The semiconductor memory device may include a voltage generator configured for generating a program voltage applied to a normal memory cell selected among the plurality of normal memory cells, and for generating a dummy word line voltage applied to the dummy memory cell in a program operation. The semiconductor memory device may include a control logic configured for controlling the voltage generator to adjust the dummy word line voltage based on the program voltage.

Abstract: A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A semiconductor device may include memory blocks having a plurality of strings including drain select transistors and memory cells electrically coupled in series between a bit line and a pipe transistor and source select transistors and memory cells electrically coupled in series between a common source line and the pipe transistor; a circuit group configured to float drain select lines electrically coupled to the drain select transistors included in unselected memory blocks and source select lines electrically coupled to the source select transistors included in the unselected memory blocks and to ground a pipe line electrically coupled to the pipe transistor when a program operation of a selected memory block among the memory blocks is performed; and a control circuit configured to control the circuit group.

Abstract: A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

Abstract: A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.

Abstract: A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.

Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.

Abstract: A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.

Abstract: A memory string includes a pass transistor, first memory cells connected in series to a drain terminal of the pass transistor, and first to kth memory cell groups connected in parallel to a source terminal of the pass transistor and each including a plurality of second memory cells connected in series. Here, ‘k’ denotes an integer that is equal to or greater than ‘2’.