Patents by Inventor Hyun Seung Yoo

Hyun Seung Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120170371
    Abstract: A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.
    Type: Application
    Filed: December 22, 2011
    Publication date: July 5, 2012
    Inventors: Seiichi ARITOME, Hyun-Seung Yoo, Sung-Jin Whang
  • Publication number: 20110204430
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Application
    Filed: April 29, 2011
    Publication date: August 25, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
  • Publication number: 20110199813
    Abstract: A non-volatile memory device having a three-dimensional (3D) structure includes a plurality of line-type horizontal electrode structures configured to include a plurality of interlayer dielectric layers and a plurality of horizontal electrodes that are alternately stacked over a substrate, a plurality of pillar-type vertical electrodes configured to protrude from the substrate while contacting sidewalls of the plurality of the horizontal electrode structures, and a memory layer interposed between the plurality of the horizontal electrode structures and the plurality of the vertical electrodes, and configured to have a resistance value that varies based on a bias applied to the plurality of the horizontal electrodes and the plurality of the vertical electrodes.
    Type: Application
    Filed: December 29, 2010
    Publication date: August 18, 2011
    Inventors: Hyun-Seung Yoo, Eun-Seok Choi
  • Patent number: 7955960
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Grant
    Filed: March 21, 2008
    Date of Patent: June 7, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Se Jun Kim, Eun Seok Choi, Kyoung Hwan Park, Hyun Seung Yoo, Myung Shik Lee, Young Ok Hong, Jung Ryul Ahn, Yong Top Kim, Kyung Pil Hwang, Won Sic Woo, Jae Young Park, Ki Hong Lee, Ki Seon Park, Moon Sig Joo
  • Publication number: 20110090737
    Abstract: A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.
    Type: Application
    Filed: October 19, 2010
    Publication date: April 21, 2011
    Inventors: Hyun-Seung Yoo, Eun-Seok Choi, Se-Jun Kim
  • Patent number: 7616496
    Abstract: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.
    Type: Grant
    Filed: June 29, 2007
    Date of Patent: November 10, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun Seok Choi, Se Jun Kim, Kyoung Hwan Park, Hyun Seung Yoo
  • Publication number: 20080230830
    Abstract: A nonvolatile memory device and a method of fabricating the same is provided to prevent charges stored in a charge trap layer from moving to neighboring memory cells. The method of fabricating a nonvolatile memory device, includes forming a first dielectric layer on a semiconductor substrate in which active regions are defined by isolation layers, forming a charge trap layer on the first dielectric layer, removing the first dielectric layer and the charge trap layer over the isolation layers, forming a second dielectric layer on the isolation layers including the charge trap layer, and forming a conductive layer on the second dielectric layer.
    Type: Application
    Filed: March 21, 2008
    Publication date: September 25, 2008
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Se Jun KIM, Eun Seok CHOI, Kyoung Hwan PARK, Hyun Seung YOO, Myung Shik LEE, Young Ok HONG, Jung Ryul AHN, Yong Top KIM, Kyung Pil HWANG, Won Sic WOO, Jae Young PARK, Ki Hong LEE, Ki Seon PARK, Moon Sig JOO
  • Publication number: 20080225595
    Abstract: A method of programming a charge trap type non-volatile memory device includes applying a program pulse to a selected memory cell, applying a detrap pulse to the selected memory cell, and applying a program verify pulse to the memory cell. The charge trap type non-volatile memory device includes a memory cell array including a charge trap memory cell, and a high voltage generator for supplying a detrap pulse to the charge trap memory cell.
    Type: Application
    Filed: June 29, 2007
    Publication date: September 18, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Eun Seok CHOI, Se Jun Kim, Kyoung Hwan Park, Hyun Seung Yoo
  • Publication number: 20080128789
    Abstract: A semiconductor memory device includes a semiconductor substrate in which junctions are formed, and a tunnel insulating layer, a charge storage layer, a blocking layer and a gate electrode pattern, which are sequentially stacked over the semiconductor substrate. The blocking layer has a structure in which a blocking insulating layer is surrounded by a high dielectric layer.
    Type: Application
    Filed: April 26, 2007
    Publication date: June 5, 2008
    Applicant: Hynix Semiconductor Inc.
    Inventors: Kyoung Hwan PARK, Eun Seok Choi, Se Jun Kim, Hyun Seung Yoo