Patents by Inventor Hyun Seung Yoo

Hyun Seung Yoo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9019767
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
    Type: Grant
    Filed: February 16, 2012
    Date of Patent: April 28, 2015
    Assignee: SK Hynix Inc.
    Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
  • Publication number: 20150099338
    Abstract: A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.
    Type: Application
    Filed: December 10, 2014
    Publication date: April 9, 2015
    Inventor: Hyun Seung YOO
  • Publication number: 20150085576
    Abstract: A semiconductor memory apparatus includes a memory block including memory cells coupled between a bit line and a source line and operating in response to voltages applied to word lines, and a peripheral circuit suitable for performing operations relating to data input and output of the memory cells, wherein the peripheral circuit is suitable for applying a precharge voltage to the bit line when word lines adjacent to a selected word line are set to a floating state.
    Type: Application
    Filed: February 25, 2014
    Publication date: March 26, 2015
    Applicant: SK hynix Inc.
    Inventors: Hyun Seung YOO, Moon Sik SEO
  • Publication number: 20150079741
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.
    Type: Application
    Filed: December 5, 2014
    Publication date: March 19, 2015
    Inventors: Eun Seok CHOI, Hyun Seung YOO
  • Patent number: 8941172
    Abstract: A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.
    Type: Grant
    Filed: July 5, 2012
    Date of Patent: January 27, 2015
    Assignee: SK Hynix Inc.
    Inventor: Hyun Seung Yoo
  • Patent number: 8912053
    Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.
    Type: Grant
    Filed: September 7, 2012
    Date of Patent: December 16, 2014
    Assignee: SK Hynix Inc.
    Inventor: Hyun-Seung Yoo
  • Publication number: 20140254281
    Abstract: A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.
    Type: Application
    Filed: May 19, 2014
    Publication date: September 11, 2014
    Applicant: SK hynix Inc.
    Inventors: Hyun-Seung YOO, Eun-Seok CHOI, Se-Jun KIM
  • Patent number: 8730727
    Abstract: A 3D non-volatile memory device includes a plate-type lower select line formed over a substrate, a lower select transistor formed in the lower select line, a plurality of memory cells stacked over the lower select transistor, an upper select transistor formed over the memory cells, and a line-type common source line formed over the substrate and spaced from the lower select line.
    Type: Grant
    Filed: October 19, 2010
    Date of Patent: May 20, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyun-Seung Yoo, Eun-Seok Choi, Se-Jun Kim
  • Patent number: 8711630
    Abstract: A programming method of a non-volatile memory device that includes a string of memory cells with a plurality of floating gates and a plurality of control gates disposed alternately, wherein each of the memory cells includes one floating gate and two control gates disposed adjacent to the floating gate and two neighboring memory cells share one control gate. The programming method includes applying a first program voltage to a first control gate of a selected memory cell and a second program voltage that is higher than the first program voltage to a second control gate of the selected memory cell, and applying a first pass voltage to a third control gate disposed adjacent to the first control gate and a second pass voltage that is lower than the first pass voltage to a fourth control gate disposed adjacent to the second control gate.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: April 29, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Seiichi Aritome, Hyun-Seung Yoo, Sung-Jin Whang
  • Patent number: 8675404
    Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.
    Type: Grant
    Filed: May 18, 2012
    Date of Patent: March 18, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Seung Yoo, Sung-Joo Hong, Seiichi Aritome, Seok-Kiu Lee, Sung-Kye Park, Gyu-Seog Cho, Eun-Seok Choi, Han-Soo Joo
  • Patent number: 8637913
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.
    Type: Grant
    Filed: November 25, 2011
    Date of Patent: January 28, 2014
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyun-Seung Yoo, Eun-Seok Choi
  • Publication number: 20130234234
    Abstract: A method for fabricating a non-volatile memory device includes forming a stacked structure where a plurality of inter-layer dielectric layers and a plurality of second sacrificial layers are alternately stacked over a substrate, forming a channel layer that is coupled with a portion of the substrate by penetrating through the stacked structure, forming a slit that penetrates through the second sacrificial layers by selectively etching the stacked structure, removing the second sacrificial layers that are exposed through the slit, forming an epitaxial layer over the channel layer exposed as a result of the removal of the second sacrificial layers, and forming a gate electrode layer filling a space from which the second sacrificial layers are removed, and a memory layer interposed between the gate electrode layer and the epitaxial layer.
    Type: Application
    Filed: September 7, 2012
    Publication date: September 12, 2013
    Inventor: Hyun-Seung YOO
  • Patent number: 8482055
    Abstract: A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.
    Type: Grant
    Filed: November 28, 2011
    Date of Patent: July 9, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-Seok Choi, Hyun-Seung Yoo
  • Publication number: 20130128660
    Abstract: A reading method of a non-volatile memory device that includes a plurality memory cells that each include one floating gate and two control gates disposed adjacent to the floating gate on two alternate sides of the floating gate, respectively, and two adjacent memory cells share one control gate, the reading method comprising applying a read voltage to control gates of a selected memory cell, applying a second pass voltage to alternate control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates next to the selected memory cell, and applying a first pass voltage that is lower than the second pass voltage to alternate the control gates of the memory cells different from the control gates of the selected memory cells starting from the control gates secondly next to the selected memory cell.
    Type: Application
    Filed: May 18, 2012
    Publication date: May 23, 2013
    Inventors: Hyun-Seung YOO, Sung-Joo HONG, Seiichi ARITOME, Seok-Kiu LEE, Sung-Kye PARK, Gyu-Seog CHO, Eun-Seok CHOI, Han-Soo JOO
  • Publication number: 20130113033
    Abstract: A non-volatile memory device in accordance with one embodiment of the present invention includes a substrate including a P-type impurity-doped region, a channel structure comprising a plurality of interlayer insulating layers that are alternately stacked with a plurality of channel layers on the substrate, a P-type semiconductor pattern that contacts sidewalls of the plurality of channel layers, wherein a lower end of the P-type semiconductor pattern contacts the P-type impurity-doped region, and source lines that are disposed at both sides of the P-type semiconductor pattern and contact the sidewalls of the plurality of channel layers.
    Type: Application
    Filed: September 11, 2012
    Publication date: May 9, 2013
    Inventors: Eun-Seok CHOI, Hyun-Seung Yoo
  • Publication number: 20130099306
    Abstract: A three-dimensional (3-D) nonvolatile memory device includes a support protruded from a surface of a substrate and configured to have an inclined sidewall; channel structures each configured to comprise interlayer insulating layers and channel layers which are alternately stacked over the substrate including the support, bent along the inclined sidewall of the support, wherein each of the channel structures comprises a cell region and a contact region, and the channel layers are exposed in the contact region; select lines formed over the channel structures; and a pillar type channels coupled to respective channel layers at the contact region and penetrating the select lines.
    Type: Application
    Filed: September 13, 2012
    Publication date: April 25, 2013
    Applicant: SK HYNIX INC.
    Inventors: Eun Seok CHOI, Hyun Seung YOO
  • Publication number: 20130009235
    Abstract: A non-volatile memory device includes first and second vertical channel layers generally protruding upwardly from a semiconductor substrate substantially in parallel; a first gate group configured to include a plurality of memory cell gates which are stacked substantially along the first vertical channel layer and are isolated from each other with an interlayer insulating layer interposed substantially between the memory cell gates; a second gate group configured to include a plurality of memory cell gates which are stacked substantially along the second vertical channel layer and are isolated from each other with the interlayer insulating layer interposed substantially between the memory cell gates; a pipe channel layer configured to couple the first and the second vertical channel layers; and a channel layer extension part generally extended from the pipe channel layer to the semiconductor substrate and configured to couple the pipe channel layer and the semiconductor substrate.
    Type: Application
    Filed: July 5, 2012
    Publication date: January 10, 2013
    Applicant: SK Hynix Inc.
    Inventor: Hyun Seung YOO
  • Publication number: 20120299076
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate and comprising a first region that is doped with first impurities and a second region that is disposed under the first region, a plurality of memory cells and a selection transistor stacked over the substrate along the channel, and a diffusion barrier interposed between the first region and the second region, wherein a density of the first impurities is higher than a density of impurities of the second region.
    Type: Application
    Filed: November 25, 2011
    Publication date: November 29, 2012
    Inventors: Hyun-Seung YOO, Eun-Seok Choi
  • Publication number: 20120213009
    Abstract: A nonvolatile memory device includes a channel vertically extending from a substrate, a plurality of memory cells stacked along the channel; a source region connected to a first end portion of the channel, and a bit line connected to a second end portion of the channel, wherein the first end portion of the channel that adjoins the source region is formed as an undoped semiconductor layer or a semiconductor layer doped with P-type impurities.
    Type: Application
    Filed: February 16, 2012
    Publication date: August 23, 2012
    Inventors: Seiichi ARITOME, Hyun-Seung YOO, Sung-Jin WHANG
  • Publication number: 20120168849
    Abstract: A non-volatile memory device includes a substrate including a resistor layer having a resistance lower than that of a source line, channel structures including a plurality of inter-layer dielectric layers that are alternately staked with a plurality of channel layers over the substrate, and the source line configured to contact sidewalls of the channel layers, where a lower end of the source line contacts the resistor layer.
    Type: Application
    Filed: November 28, 2011
    Publication date: July 5, 2012
    Inventors: Eun-Seok CHOI, Hyun-Seung Yoo