Abstract: A semiconductor device is provided having an input driver and an output receiver connected by a bus line, the bus line including pulse generating and driver circuitry responsive to threshold levels of voltage change so as to perform high speed switching which compensates for the load of the bus line.

Abstract: A pad signal detecting circuit for detecting a reference voltage input to a pad of a semiconductor device. This invention may be used in high speed terminated interfaces using a reference voltage, such as those using stub series termination logic (SSTL). The invention allows the manufacture of semiconductor devices having more than one type of interface, because the device can sense the type of interface which is connected to the pad and activate the appropriate interface circuitry. This feature eliminates the need to manufacture different devices for different types of interfaces, and it facilitates high volume and low cost production of semiconductor devices that are compatible with more than one type of interface circuitry.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A self refresh circuit for an integrated circuit memory device includes a programmable refresh circuit, a plurality of counters, and a refresh cycle selection circuit. The programmable refresh circuit can be electrically programmed to generate one of a plurality of refresh control signals. A first one of the counters generates a first oscillating output signal having a first predetermined period and each successive counter generates a respective oscillating output signal having a respective period twice that of a respective preceding counter. The refresh cycle selection circuit selects a self refresh cycle from one of the oscillating output signals in response to the refresh control signal generated by the at least one programmable refresh circuit. Related methods are also disclosed.

Abstract: A semiconductor memory device reduces the distance occupied between a data path circuit and pads, and minimizes the length of data lines and main input/output lines, thereby improving an operating speed thereof. The semiconductor memory device includes a memory array divided into four array blocks which are independently arranged; a plurality of pads disposed in an area between the upper array blocks and the respective lower array blocks; a data path control circuit disposed in an area between the left array blocks and the respective right array blocks; a data path circuit disposed in a middle center area among the four array blocks; a plurality of data lines connecting the pads to the data path circuit; and a plurality of main input/output lines connecting the memory array to the data path circuit. In this configuration, a distance between the data lines and the main input/output lines and the data path circuit can be minimized.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

Abstract: A bit line sensing circuit of a semiconductor memory device is disclosed which includes a pull-up control signal generator that enables the peak current to be small by supplying to the P sense amplifier a pull-up voltage of the low level in an initial sensing process. When the peak current is stabilized, the pull-up control signal generator then reduces the time required for raising the pull-up voltage by very quickly raising the voltage of the pull-up control signal. This results in the advantages that the peak current can be greatly reduced without slowing sensing speed, and voltage noise caused from peak currents can be eliminated.

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU).

Abstract: A semiconductor memory device for processing data in synchronization with a system clock applied from the exterior includes a circuit for generating a write latency control signal, a circuit for generating one active information enlarged signal from a plurality of active information signals generated in response to a column related control signal supplied from the exterior, and a circuit for holding internal operations of a column address counter, a burst length counter and a data transfer switching circuit for a prescribed time in which the active information enlarged signal is in an active state.

Abstract: A data output buffer of a semiconductor memory device using a clock having a fixed period from outside. The data output buffer has a data input part controlled and synchronized with a clock, for inputting data; a data latch device for latching data output through the data input part to thereby set up a predetermined delay time; a control signal input part controlled by the clock, for inputting a control signal; a latch controller for latching the control signal output through the control signal input part during a given time; a data output driver for receiving an output signal from the data latch device, the data output driver being controlled by the output signal of the latch controller; and an output device connected to the data output driver, for providing the data.

Abstract: A semiconductor memory device for alternately selecting two groups of input/output lines according to a predetermined column address. A first group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the first group, and a second group of a number of the input/output line pairs is driven by activation of any one of the selection signals within the second group. Furthermore, the input/output line pairs within the second group are precharged and equalized when the input/output line pairs within the first group are driven, and the input/output line pairs within the first group are precharged and equalized when the input/output line pairs within the second group are driven.

Abstract: The invention is to provide a data input buffer which can attain stably an input trip level regardless of a variation of power source voltage, for use in a semiconductor memory device, and particularly to provide a data input buffer which is not affected by a variation of power source voltage. The data input buffer circuit comprises a conductive passage, coupled between the power source voltage and a level sensing node, for adjusting the amount of an current according to a level of input voltage; and an insulation gate field effect transistor, with one end of channel of the transistor connected to the conductive passage, other end of channel of the transistor connected to ground voltage terminal and a gate of the transistor to which voltage is applied according to a level of the power source voltage.

Abstract: A row redundancy circuit for repairing a defective cell of a memory cell array in a semiconductor memory device comprising an address selector 300 for receiving two or more of address bit pairs, of an address bit pair group, designating the defective cell to selectively output one of the two or more address bit pairs, a fuse box 100 for storing the information of the remaining address bits of the address bit pair group, except the address bits of the selected address bit pair output by the address selector, and at least a redundant decoder 200, 200A for decoding the output signals of the address selector and fuse box, thereby maximizing the row redundancy efficiency.

Abstract: This invention provides an input protection device having, within a body of semiconductor material, parallel, doped regions providing an input circuit and a charge collection area for protecting against static electricity charges at the input stage of semiconductor devices, the device including a low resistance layer formed on the body overlying the input circuit which is connected to an input pad on the body. Shortening the input signal delay time is thus attained.