Abstract: Disclosed herein is an interdigitation-type diffractive light modulator. In the interdigitation-type diffractive light modulator of the present invention, each of a pair of ribbons has a plurality of diffractive branches which are arranged in a comb shape, and the diffractive branches of the ribbons interdigitate with each other. Furthermore, the respective ribbons moves upwards and downwards or, alternatively, one ribbon moves upwards and downwards, so that the diffractive branches of the ribbons which interdigitate with each other form a stepped structure, thus diffracting incident light.

Abstract: Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.

Abstract: Disclosed is a fishbone diffraction-type light modulator. In the fishbone diffraction-type light modulator, a lower micromirror is provided on a silicone substrate, and an upper micromirror is spaced apart from the silicone substrate and has a plurality of openings through both sides thereof. The upper micromirror and the lower micromirror deposited on the silicone substrate form pixels.

Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.

Abstract: A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Abstract: Output driving circuit including at least one or more than one level shifter for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit while maintaining a duty ratio of the input signal constant, and an output driving unit for forwarding the input signal to the outside of the integrated circuit under the control of an output enable signal, thereby permitting application to the integrated circuit operative at a high speed, readily.

Abstract: Circuit for correcting a duty factor of a clock signal, including a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180° and 360° clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180° and 360° clock generating control signals.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: The present invention relates to substantially spherical carbon nano particle having a novel structure, which comprises a plurality of layers formed by planar and curved graphene sheets which are connected to each other and a hollow inner core. The carbon nano particles of the present invention has field emission properties comparable to those of carbon nanotubes and can be advantageously used in such industries as aerospace, biotechnology, environmental energy, materials, medicine, electronics.

Abstract: Circuit for correcting a duty factor of a clock signal, including a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180° and 360° clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180° and 360° clock generating control signals.

Abstract: Output driving circuit including at least one or more than one level shifter for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit while maintaining a duty ratio of the input signal constant, and an output driving unit for forwarding the input signal to the outside of the integrated circuit under the control of an output enable signal, thereby permitting application to the integrated circuit operative at a high speed, readily.

Abstract: A method for detecting a phase difference between an input clock signal and a feedback output clock signal, correcting by delaying time corresponding to the phase difference, and generating a phase control signal delayed for a time period corresponding to the phase difference is disclosed.

Abstract: A variable input/output control device in a synchronous semiconductor memory device including a plurality of first prefetch units to prefetch data from an input buffer, a plurality of second prefetch units to prefetch data from a memory core and a control signal generator for generating a control signal in response to command signals to select one of the plurality of first prefetch units and one of the plurality of second prefetch units.

Abstract: A semiconductor memory device including an N-bit prefetch unit, a plurality of data output drivers to output data from the N-bit prefetch unit and a control signal generator for generating a plurality of control signals in response to command signals, wherein the plurality of data output drivers are driven by the control signals.

Abstract: A method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock in a high speed memory device, includes the steps of receiving the external signal to generate a full-swing level signal, dividing the full-swing level signal into a first signal and a second signal in synchronization with the data strobe signal, wherein the first signal is activated in synchronization with rising edges of the data strobe signal and the second signal is activated in synchronization with falling edges of the data strobe signal, aligning the first signal and the second signal with one of both edges of the data strobe signal, and aligning the aligned first and second signals with one of both edges of a main clock.

Abstract: A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: A variable input/output control device in a synchronous semiconductor memory device including a plurality of first prefetch units to prefetch data from an input buffer, a plurality of second prefetch units to prefetch data from a memory core and a control signal generator for generating a control signal in response to command signals to select one of the plurality of first prefetch units and one of the plurality of second prefetch units.

Abstract: A semiconductor memory device including an N-bit prefetch unit, a plurality of data output drivers to output data from the N-bit prefetch unit and a control signal generator for generating a plurality of control signals in response to command signals, wherein the plurality of data output drivers are driven by the control signals.