Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: The present invention relates to substantially spherical carbon nano particle having a novel structure, which comprises a plurality of layers formed by planar and curved graphene sheets which are connected to each other and a hollow inner core. The carbon nano particles of the present invention has field emission properties comparable to those of carbon nanotubes and can be advantageously used in such industries as aerospace, biotechnology, environmental energy, materials, medicine, electronics.

Abstract: A method for detecting a phase difference between an input clock signal and a feedback output clock signal, correcting by delaying time corresponding to the phase difference, and generating a phase control signal delayed for a time period corresponding to the phase difference is disclosed.

Abstract: Output driving circuit including at least one or more than one level shifter for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit while maintaining a duty ratio of the input signal constant, and an output driving unit for forwarding the input signal to the outside of the integrated circuit under the control of an output enable signal, thereby permitting application to the integrated circuit operative at a high speed, readily.

Abstract: Circuit for correcting a duty factor of a clock signal, including a phase comparator for detecting a phase difference of an input clock signal having a duty factor to be corrected, and a corrected clock signal having the duty factor corrected, and generating a shift control signal, a control signal generating part for shifting a clock generating reference signal in response to the shift control signal, and delaying the clock generating reference signal for a preset time period to generate 180° and 360° clock generating control signals, and a clock signal generating part for generating a clock signal having a corrected duty factor according to the 180° and 360° clock generating control signals.

Abstract: A variable input/output control device in a synchronous semiconductor memory device including a plurality of first prefetch units to prefetch data from an input buffer, a plurality of second prefetch units to prefetch data from a memory core and a control signal generator for generating a control signal in response to command signals to select one of the plurality of first prefetch units and one of the plurality of second prefetch units.

Abstract: A semiconductor memory device including an N-bit prefetch unit, a plurality of data output drivers to output data from the N-bit prefetch unit and a control signal generator for generating a plurality of control signals in response to command signals, wherein the plurality of data output drivers are driven by the control signals.

Abstract: A method for receiving an external signal in synchronization with rising and falling edges of a data strobe signal to generate two internal signals in synchronization with one of both edges of a main clock in a high speed memory device, includes the steps of receiving the external signal to generate a full-swing level signal, dividing the full-swing level signal into a first signal and a second signal in synchronization with the data strobe signal, wherein the first signal is activated in synchronization with rising edges of the data strobe signal and the second signal is activated in synchronization with falling edges of the data strobe signal, aligning the first signal and the second signal with one of both edges of the data strobe signal, and aligning the aligned first and second signals with one of both edges of a main clock.

Abstract: A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: A semiconductor memory device including an N-bit prefetch unit, a plurality of data output drivers to output data from the N-bit prefetch unit and a control signal generator for generating a plurality of control signals in response to command signals, wherein the plurality of data output drivers are driven by the control signals.

Abstract: A variable input/output control device in a synchronous semiconductor memory device including a plurality of first prefetch units to prefetch data from an input buffer, a plurality of second prefetch units to prefetch data from a memory core and a control signal generator for generating a control signal in response to command signals to select one of the plurality of first prefetch units and one of the plurality of second prefetch units.

Abstract: An apparatus and method for decoding address signals. The apparatus generally comprises an address buffer array, a buffer controller coupled to the address buffer array, an address decoder coupled to the address buffer array and a strobe generator coupled to the address decoder and the buffer controller. The address buffer array buffers address signals in response to an address strobe from the buffer controller. The strobe generator generates a decoding strobe in response to the address strobe. The decoding strobe signals the address decoder to decode the address signals received from the address buffer array. To synchronize the arrival of the decoding strobe and the buffered address signals at the decoder, the strobe generator has one or more signal transfer characteristics in common with one or more of the address buffers. In a specific embodiment, the strobe generator has a longer signal transfer delay than any address buffer in the address buffer array.

Abstract: A data strobe buffer in SDRAM is disclosed. The data strobe buffer for a synchronous dynamic read only memory (SDRAM), comprising: a first dynamic buffer generating a first pulse at a rising edge of a data strobe signal; a second dynamic buffer generating a second pulse at a falling edge of the data strobe signal; and a block for generating an enable signal which is enabled in a range between a rising edge of an external clock signal and a logic high state of the second pulse, and providing the second dynamic buffer with the enable signal. The data strobe buffer ensures a minimum value of tDQSS parameter in DDR SDRAM even if speed of the chip increases or operation condition of the chip becomes tight, thereby preventing the data strobe buffer from being misoperated due to the damping and the fluctuation of the data strobe signal.

Abstract: An apparatus for receiving an external data strobe signal in a high-speed memory device to generate an internal data strobe signal used in a write operation therein, includes first buffering means, activated by an enable signal, for receiving the external data strobe signal having a series of pulses to output a first internal data strobe signal having a series of pulses, each pulse of the first internal data strobe signal corresponding to a rising edge of each pulse of the external data strobe signal, and second buffering means, activated by the enable signal, for receiving the external data strobe signal having a series of pulses to output a second internal data strobe signal having a series of pulses, each pulse of the second internal data strobe signal corresponding to a falling edge of each pulse of the external data strobe signal, wherein a delay to a corresponding pulse of the first internal data strobe signal from a rising edge of each pulse of the external data strobe signal is substantially identical

Abstract: Disclosed is a DDR SDRAM device which may be implemented by simply modifying a pipe counter for an SDR SDRAM device. A pipe counter comprising according to the present invention comprises: a controller for producing a counter control signal in response to rising and falling edge signals of an external clock signal; an enabling unit for producing a plurality of enable signals in response to the counter control signal and for enabling one of the enable signals during one period of the counter control signal; and a driver for receiving one of the enable signals, producing first and second pipe counter signals being synchronized with the rising and falling edge signals of the external clock signal, wherein one of the first and second pipe counter signals is activated during one period of the received enable signal.

Abstract: An apparatus for driving a cell plate line of a semiconductor memory device having a plurality of memory cells, includes: a first driving means for driving the cell plate line with a first power supply voltage; a second driving means for driving the cell plate line with a second power supply voltage higher than the first power supply voltage; and a driving control means for enabling said second driving means for a predetermined time in order to activate the cell plate line in response to a control signal from an external circuit and enabling said first driving means after the predetermined time in order to stabilize said second driving means enables, wherein the control signal is employed to select one memory cell related to the cell plate line. Thereby, the apparatus can the high-speed operation of a ferroelectric random access memory (FeRAM) by using two power supply voltage sources.

Abstract: The present invention relates to semiconductor memory device and more particularly, to a technique for stabilizing the potential of the cell plate line by using two kinds of potentials for the cell plate line driver to implement the powerful driving force and rapid operability required in case of designing the RAM using as the memory device the material having large electrostatic capacity, and for preventing the loss of I/O by using CMOS transistors in the decoder circuit which receives the cell plate line voltage by cooperating with the cell plate line driver circuit and feeds back the cell plate line voltage.

Abstract: A variable comparison voltage generation apparatus for a semiconductor memory element substitutes a variable comparison voltage amplifier for a fixed comparison voltage amplifier used for a ferroelectric substance memory. The variable comparison voltage generation apparatus according to the present invention accurately detect the data stored in the memory element with ferroelectric substance.