Abstract: The present invention relates to a load sharing device and a parallel power supply therewith. There is provided a parallel power supply, including: a plurality of power supply modules each connected to a single load in parallel to provide balanced output currents to the single load; a common voltage control signal output unit that generates a common voltage control signal from output voltages of the plurality of power supply modules and outputs the common voltage control signals to the plurality of power supply modules; and output voltage control units that are provided in the respective plurality of power supply modules to detect output currents of the plurality of power supply modules and to control output voltages of the plurality of power supply modules according to the detected signals, controlling the output voltages to be in a predetermined voltage range according to the common voltage control signals.

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.

Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: Provided is an apparatus for acquiring a digital X-ray image that radiates X-ray on a patient's part by using a high sensitivity imaging plate (IP), reads the radiated patient's part, acquires a signal including patient information and image information regarding a patient, converts the signal into a digital signal, and links the digital signal to external equipment.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: Digital signal processing (“DSP”) circuit blocks are provided that can more easily work together to perform larger (e.g., more complex and/or more arithmetically precise) DSP operations if desired. These DSP blocks may also include redundancy circuitry that facilitates stitching together multiple such blocks despite an inability to use some block (e.g., because of a circuit defect). Systolic registers may be included at various points in the DSP blocks to facilitate use of the blocks to implement systolic form, finite-impulse-response (“FIR”), digital filters.

Abstract: A mobile system, a service system, and a service providing method for securely transmitting private information for use in a service are provided. The mobile system maintains at least one user data and identification data with respect to the user data used for processing at least one service, sets a session key for the service system, and encrypts service data identified based on the identification data to transmit to the service system.

Abstract: A mobile system, a service system, and a key authentication method to manage a key in a local wireless communication are provided. The mobile system and the service system may generate a hash value with respect to a public key of the service system using an identical hash function, and output a result corresponding to the hash value.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: A mobile privacy protection system using a proxy, a proxy device, and a mobile privacy protection method are provided. The mobile privacy protection system includes: an electronic tag to store predetermined tag information; a proxy device to adjust a privacy level of the electronic tag; and a home server to create new tag information in response to a request from the proxy device wherein the new tag information is used to adjust the privacy level.

Abstract: A tag authentication method, and a tag and reader performing the method are provided. The tag authentication method, including: a reader generating a first random number and transmitting the first random number to a tag; the reader receiving a second random number and a first verification value from the tag; the reader computing a second verification value based on the first random number and the second random number; and the reader comparing the first verification value and the second verification value.

Abstract: Disclosed is a method for decoding received signals on communication channels between at least one transmit antenna and plural receive antennas in a space-time coded direct sequence (DS)-CDMA communication system. The decoding method includes steps of: adjusting the step-size which is an update unit for the tap weight vector for despreading received signals; updating the tap weight vector using the step-size; and despreading the received signals using the tap weight vector. According to the decoding method, the optimal performance can be achieved because the tap weight vector and the step-size are adaptively updated according to changes of communication environment. Such superior performance is more remarkable as the number of receive antennas and transmit antennas increases.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: Techniques are provided for calibrating parallel on-chip termination (OCT) impedance circuits. An on-chip termination (OCT) calibration circuit generates first calibration codes and second calibration codes. The first calibration codes control the conductive states of first transistors that are coupled in parallel between a supply voltage and a first terminal. The second calibration codes control the conductive states of second transistors that are coupled in parallel between the first terminal and ground. The OCT calibration circuit selects a first calibration code and a second calibration code and transmits the selected calibration codes to third and fourth transistors to control a parallel on-chip termination impedance at a pin.

Abstract: A method and system for performing a distributed verification with respect to measurement data in a sensor network. The method of performing the distributed verification with respect to measurement data in a sensor network includes: verifying, by an aggregator, the measurement data received from each of a plurality of sensors; generating, by the aggregator, verification request data by using the verified measurement data; transmitting the verification request data to a verifier; and verifying, by the verifier, the aggregator via a predetermined number of sensors of the plurality of sensors and the verification request data. The method of performing a distributed verification with respect to measurement data in a sensor network further includes transmitting, by the aggregator, an aggregation result with respect to the measurement data to a base station when the aggregator is verified; and verifying, by the base station, the aggregation result.

Abstract: Pop-up Business Card by this invention is characterized by—information printing part which contains the information of the card such as the company name, personal name, and contact number, —main folding line generated by the line-drawing process on one side of the card so that part of the card can be folded, —cutting-line pattern which contains cutting-lines formed from the main folding-line to the other side of the card, —the 1st folding-line pattern generated by line-drawing process on one side of the card so as to be juxtaposed with the cutting-line pattern, —the 2nd folding-line pattern generated by line-drawing process on the other side of the card paper so as to be juxtaposed with the above cutting-line pattern, *—the generation of the solid figures on the card when it is folded according to the above main folding-line, cutting-line pattern, the 1st folding-line pattern, and 2nd folding-line pattern, —solid figures reversibly popped up when the card is opened from the folded state along the main folding

Abstract: A key calculation method and a shared key generation method, the key calculation method including: generating two keys to perform a key calculation; calculating a first value based on coefficients having an identical coefficient value among coefficients included in each of the two keys; and performing a coordinates operation or an exponentiation operation based on the first value, wherein the calculating of the first value is performed with respect to each of coefficient values included in the two keys, excluding 0.

Abstract: A batch verification apparatus and method wherein, the method includes: generating a plurality of secret keys, a plurality of public keys corresponding to the plurality of secret keys, and a plurality of verification values corresponding to the plurality of public keys; calculating a first batch verification value based on the plurality of verification values; calculating a second batch verification value based on the plurality of secret keys and the plurality of verification values; comparing the first batch verification value and the second batch verification value; and determining that a batch of the received plurality of verification values is verified when the first batch verification value is equal to the second batch verification value.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.