Abstract: A batch verification apparatus and method wherein, the method includes: generating a plurality of secret keys, a plurality of public keys corresponding to the plurality of secret keys, and a plurality of verification values corresponding to the plurality of public keys; calculating a first batch verification value based on the plurality of verification values; calculating a second batch verification value based on the plurality of secret keys and the plurality of verification values; comparing the first batch verification value and the second batch verification value; and determining that a batch of the received plurality of verification values is verified when the first batch verification value is equal to the second batch verification value.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: A distributed Rivest Shamir Adleman (RSA) signature generation method in an ad-hoc network and a node of an ad-hoc network. The distributed RSA signature generation method in an ad-hoc network includes distributing key share information, which is generated using a maximum distance separable (MDS) code and a random symmetric matrix, to a plurality of nodes; generating, in a fewer number of nodes than the plurality of nodes, a partial signature using the distributed key share information; transmitting the partial signature to a signature generation node; and generating an RSA signature using the partial signature, in the signature generation node.

Abstract: A method of protecting a broadcast frame, the method comprising broadcasting a beacon and a maintenance beacon frame (MBF) from an access point (AP) to a plurality of terminals during a maintenance beacon waiting period (MBWP); and broadcasting broadcast management frames (BMFs) from the AP to the plurality of terminals during a broadcast management frame waiting period (BMFWP), wherein the MBF comprises a BMFs message integrity code (MIC) field including a BMFs MIC calculated from concatenated BMFs to be sent in a current beacon interval.

Abstract: A distributed Rivest Shamir Adleman (RSA) signature generation method in an ad-hoc network and a signature generation node are provided, including steps for distributing key information to a plurality of nodes using an RSA parameter and a maximum distance separable (MDS) code, in a dealer node, generating a partial signature using the key information and transmitting the generated partial signature to a signature generation node, in the plurality of nodes, and generating an RSA signature using the partial signature, in the signature generation node, wherein the RSA signature is generated using the partial signature, received from a fewer number of nodes than the entire plurality of nodes.

Abstract: A public key generation method in Elliptic Curve Cryptography (ECC), and a public key generation system performing the method are provided. The public key generation method includes reducing a sequence length of the signed ternary ?-adic representation of the private key ‘k’ using properties of an elliptic curve, representing a reduced secret key ‘k’ in a signed ternary ?-adic representation; and computing a public key kP by multiplying the ?-adic representation of the private key ‘k’ whose sequence length is reduced on point P on the elliptic curve.

Abstract: A method for generating, operating, and using a sparse w-NAF key for encryption is disclosed. The method for generating a key comprises generating a string of a number of coefficients, in which at most one coefficient, excluding 0, among a consecutive w number of coefficients, corresponds to a positive odd integer equal to or less than 2w (w being a natural number equal to or more than 2); and outputting the generated string as a key. Accordingly, an encryption is executed through an exponential operation or scalar multiplication using a sparse w-NAF key having the scarce coefficients, excluding 0, such that an encryption pace is improved.

Abstract: A level conversion architecture that accommodates signals traveling between logic blocks operating at corresponding voltage levels is provided. The architecture includes pass gates connected in series between the logic blocks. One of the gates of the pass gates is supplied with a selectable gate voltage supply. The selectable gate voltage supply is selected from a plurality of voltages based on a configuration random access memory (CRAM) setting. In one embodiment, a half latch is connected to one of the pass gates. In this embodiment, the half latch is part of a feedback loop to minimize power leakage of a logic element in one of the logic blocks. A method for managing power consumption and providing voltage level conversion between regions of an integrated circuit is also provided.

Abstract: A key generation method for self-configuration is provided which includes selecting existing nodes as many as a predefined reference number t from nodes which configure a network; transmitting a partial key request message to the selected existing nodes; and generating a node key based on randomized partial keys received in response to the partial key request. Accordingly, when a new node intends to join the network, the existing nodes forming the network can allocate a node key to the new node by themselves. Also, whether the node key of the new node is compromised or not can be verified using the error-checking witness.

Abstract: Techniques are provided for calibrating on-chip termination impedances on integrated circuits. An on-chip termination (OCT) calibration circuit generates calibration codes that selectively control the conductive states of a set of transistors coupled in parallel. The OCT calibration circuit selects a calibration code that causes the impedance of the transistors to be near a matching impedance. The selected calibration code controls an on-chip termination impedance at a pin. According to some embodiments, the OCT calibration circuit compares a signal from the transistors to two or more reference signals to improve the tolerance range of the calibrated on-chip termination impedance. According to other embodiments, the OCT calibration circuit selects a calibration code based on a signal from the transistors after an extra transistor is turned on by a control signal. The control signal is not used to control the on-chip termination impedance.

Abstract: A semiconductor device including a semiconductor substrate, an integrated circuit on the semiconductor substrate, an insulation layer covering the integrated circuit, and a plurality of metal line patterns on the insulation layer. First and second adjacent metal line patterns of the plurality of metal line patterns are spaced apart from each other by a space, and each of the first and second adjacent metal line patterns has at least one slit.

Abstract: An interconnect delay fault test controller and a test apparatus using the same wherein an update operation and a capture operation may be carried out in one interval of a system clock or a core clock when carrying out an interconnect delay fault test between an IEEE P1500 wrapped cores in a SoC as well as an interconnect wire on a board based on an IEEE 1149.1, and wherein the interconnect delay fault test using different system clocks or core clocks may be carried out simultaneously in one test cycle corresponding to each system clock or core clock even when multiple system clocks or core clocks exists is disclosed.

Abstract: A semiconductor device and a method of manufacturing the same which yields high reliability and a high manufacturing yield. The semiconductor device includes a metal line layer having a plurality of metal line patterns spaced apart from each other, and at least one underlying layer under the metal line layer, wherein the space between two adjacent metal line patterns has a sufficient width to prevent a crack from occurring in one or more of the underlying layers. The cracking of an underlying layer may also be prevented by providing a slit in a direction parallel to the space between two adjacent metal line patterns at a sufficient distance from the space between the two adjacent metal line patterns.

Abstract: A spin transistor having wide ON/OFF operation margin and producing less noise is provided. The spin transistor includes a substrate having a channel, a source, a drain and a gate formed on the substrate. The source and the drain are formed to have magnetization directions perpendicular to the length direction of the channel. The ON/OFF operations of the spin transistor can be controlled by generating a spin-orbit coupling induced magnetic field to have a direction parallel or anti-parallel to the magnetization directions of the source and the drain.

Abstract: Disclosed herein is an interdigitation-type diffractive light modulator. In the interdigitation-type diffractive light modulator of the present invention, each of a pair of ribbons has a plurality of diffractive branches which are arranged in a comb shape, and the diffractive branches of the ribbons interdigitate with each other. Furthermore, the respective ribbons moves upwards and downwards or, alternatively, one ribbon moves upwards and downwards, so that the diffractive branches of the ribbons which interdigitate with each other form a stepped structure, thus diffracting incident light.

Abstract: Disclosed herein is a multilayered chip capacitor array, including a capacitor body having a plurality of dielectric layers, a plurality of pairs of first and second inner electrodes which are formed on the plurality of dielectric layers such that one electrode of one pair of inner electrodes faces the other electrode of the one pair of inner electrodes with one of the plurality of dielectric layers interposed therebetween, at least one first outer terminal and a plurality of second outer terminals formed on at least one surface of a top surface and a bottom surface of the capacitor body, and at least one first conductive via and a plurality of second conductive vias formed in a stacking direction of the capacitor body and connected to the first outer terminal and the second outer terminal, respectively.

Abstract: Disclosed is a fishbone diffraction-type light modulator. In the fishbone diffraction-type light modulator, a lower micromirror is provided on a silicone substrate, and an upper micromirror is spaced apart from the silicone substrate and has a plurality of openings through both sides thereof. The upper micromirror and the lower micromirror deposited on the silicone substrate form pixels.

Abstract: An embodiment of the present invention provides a programmable logic device (“PLD”) including a redundancy architecture adapted to selective route signals via first or second staggered vertical lines. Other embodiments provide configuration logic and programs for determining routing selections. Other embodiments provide proximate grouping of vertical lines driven from a same row. Other embodiments provide definition of spare row locations once defective row locations are known.

Abstract: A programmable logic device and associated method is provided with repairable regions. In one aspect, general routing interconnect lines are segmented within repairable regions. In another aspect, IO bus lines and associated circuitry are provided that accommodate redundancy in a staggered segmented architecture. In another aspect, a dedicated routing architecture between particular logic regions accommodates shifting to define and utilize repairable regions. Principles of other aspects are illustrated and described in the context of several exemplary embodiments of aspects of the invention.

Abstract: Output driving circuit including at least one or more than one level shifter for receiving an input signal to be provided to an outside of an integrated circuit and shifting a voltage level of the input signal to a voltage level required at the outside of the integrated circuit while maintaining a duty ratio of the input signal constant, and an output driving unit for forwarding the input signal to the outside of the integrated circuit under the control of an output enable signal, thereby permitting application to the integrated circuit operative at a high speed, readily.