Patents by Inventor Hyung Dong Lee

Hyung Dong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11227211
    Abstract: A neuromorphic device is provided. The neuromorphic device may include a plurality of pre-synaptic neuron circuits, a plurality of post-synaptic neuron circuits, and a plurality of synapses. Each of the synapses may be electrically connected to the plurality of pre-synaptic neuron circuits and a corresponding one of the plurality of post-synaptic neuron circuits. Each of the plurality of synapses may include a plurality of synapse cells. Each of the synapse cells may be electrically connected to a corresponding one of the plurality of pre-synaptic neuron circuits through a corresponding one of a plurality of row lines, respectively. Each of the synapse cells may be electrically connected to the corresponding one of the plurality of post-synaptic neuron circuits through one common column line.
    Type: Grant
    Filed: September 26, 2017
    Date of Patent: January 18, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 11210577
    Abstract: A neuromorphic device includes a pre-synaptic neuron, a synapse electrically coupled to the pre-synaptic neuron through a row line, and a post-synaptic neuron electrically coupled to the synapse through a column line. The post-synaptic neuron includes an integrator, a comparator, and an error corrector including an error detector and a correction signal generator. The comparator and the error corrector receive an output of the integrator.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: December 28, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 11195087
    Abstract: A neuromorphic device having a synapse array is provided. The synapse array of the neuromorphic device may include an input neuron; an output neuron; and a synapse. The synapse may include a plurality of ferroelectric field effect transistors electrically connected to each other in parallel.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 7, 2021
    Assignee: SK HYNIX INC.
    Inventor: Hyung-Dong Lee
  • Publication number: 20210320258
    Abstract: Provided are compound represented by Formula 1, an organic electric element including a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and electronic device thereof, and by including the compound represented by Formula 1 in the organic material layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time of the organic electric element can be improved.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Hyun Ji OH, Soung Yun MUN, Sun Hee LEE, Hyung Dong LEE, Byoung Yeop KANG, Ui Sik KWON
  • Patent number: 11145363
    Abstract: A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.
    Type: Grant
    Filed: May 18, 2020
    Date of Patent: October 12, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung Dong Lee
  • Patent number: 11106971
    Abstract: A neuromorphic device may include a pre-synaptic neuron, a row line extending from the pre-synaptic neuron in a row direction, a post-synaptic neuron, a column line extending from the post-synaptic neuron in a column direction, and a synapse coupled between the row line and the column line. The synapse may be disposed in an intersection region between the row line and the column line. The post-synaptic neuron may include a subtracting circuit.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: August 31, 2021
    Assignee: SK Hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 11093823
    Abstract: A neuromorphic device may include: a pre-synaptic neuron; a synapse electrically connected with the pre-synaptic neuron through a row line; and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a first inverter, the first inverter comprising a first pull-up transistor and a first pull-down transistor, a body of the first pull-up transistor and a body of the first pull-down transistor being electrically connected with a first output node of the first inverter.
    Type: Grant
    Filed: May 15, 2017
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Publication number: 20210217472
    Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
    Type: Application
    Filed: March 26, 2021
    Publication date: July 15, 2021
    Applicant: SK hynix Inc.
    Inventors: Ki Won LEE, Seok Man HONG, Tae Hoon KIM, Hyung Dong LEE
  • Publication number: 20210184129
    Abstract: Provided is a novel mixture capable of improving luminous efficiency, stability, and lifespan of an element, an organic electric element using the same, and an electronic device therefor.
    Type: Application
    Filed: May 3, 2019
    Publication date: June 17, 2021
    Applicant: DUK SAN NEOLUX CO., LTD
    Inventors: Soung Yun MUN, Nam Geol LEE, Sun Hee LEE, Hyung Dong LEE, Jin Bae JEON
  • Patent number: 11037052
    Abstract: A method reads data from a synapse which includes a transistor and a variable resistor. The transistor has a gate electrode, a first electrode and a second electrode. The variable resistor has a first electrode connected to the second electrode of the transistor. The method includes applying a read voltage to the gate electrode of the transistor, applying a pre-synaptic voltage to the first electrode of the transistor, and applying a post-synaptic voltage to a second electrode of the variable resistor. The read voltage is lower than the threshold voltage of the transistor.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: June 15, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 11017286
    Abstract: A neuromorphic device may include a pre-synaptic neuron, a row line extending in a row direction from the pre-synaptic neuron, a post-synaptic neuron, a column line extending in a column direction from the post-synaptic neuron, and a synapse disposed at an intersection region between the row line and the column line. The synapse may include a first node electrically connected with the row line, a second node electrically connected with the column line, and a variable resistor and a first transistor electrically coupled between the first node and the second node. The variable resistor and the first transistor may be electrically connected with each other in parallel.
    Type: Grant
    Filed: July 25, 2017
    Date of Patent: May 25, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 10978147
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: April 13, 2021
    Assignee: SK hynix Inc.
    Inventors: Hyung Dong Lee, Tae Hoon Kim
  • Patent number: 10964382
    Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: March 30, 2021
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Seok Man Hong, Tae Hoon Kim, Hyung Dong Lee
  • Publication number: 20210082501
    Abstract: A memory device includes: first conductive lines extending in a first direction; second conductive lines extending in a second direction intersecting the first direction; a plurality of memory cells disposed at intersection portions of the first conductive lines and the second conductive lines; first selection transistors respectively connected to the first conductive lines, the first selection transistors constituting a plurality of groups; and first discharge circuits respectively connected to the plurality of groups of first selection transistors, each of the first discharge circuits discharging a group of first conductive lines corresponding thereto among the first conductive lines in response to a gate control signal.
    Type: Application
    Filed: May 18, 2020
    Publication date: March 18, 2021
    Inventor: Hyung Dong LEE
  • Publication number: 20210074767
    Abstract: A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.
    Type: Application
    Filed: April 20, 2020
    Publication date: March 11, 2021
    Inventor: Hyung Dong LEE
  • Publication number: 20210066393
    Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
    Type: Application
    Filed: April 28, 2020
    Publication date: March 4, 2021
    Inventors: Si Jung YOO, Tae Hoon KIM, Hyung Dong LEE
  • Patent number: 10902316
    Abstract: A neuromorphic device is provided. The neuromorphic device may include a pre-synaptic neuron, a synapse electrically connected with the pre-synaptic neuron through a row line, and a post-synaptic neuron electrically connected with the synapse through a column line. The post-synaptic neuron may include a post-neuron circuit and a post-neuron transfer function circuit electrically connected to the column line. The post-neuron transfer function circuit may include a first inverting circuit including at least one first pull-up transistor and at least two first pull-down transistors, the pull-down transistors being electrically connected with each other in parallel.
    Type: Grant
    Filed: December 19, 2017
    Date of Patent: January 26, 2021
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Publication number: 20210013420
    Abstract: Provided are a compound represented by Formula 1, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode, and an electronic device thereof, wherein by comprising compound represented by Formula 1 in the organic material layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time, in particular, life time can be improved.
    Type: Application
    Filed: July 10, 2020
    Publication date: January 14, 2021
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Ki Ho SO, Hyung Dong LEE, Dae Hwan OH, Won Sam KIM, Byoung Yeop KANG
  • Patent number: 10839901
    Abstract: A semiconductor memory includes bit lines, word lines, memory cells coupled between the bit lines and the word lines, and a sensing circuit configured to sense a state of a selected memory cell. During a read operation of the selected memory cell, the electronic device is configured to precharge a selected word line to a first voltage, to precharge an unselected word line to a second voltage, to float the selected word line and the unselected word line, to apply a bit line voltage a selected bit line, to adjust a voltage level of the unselected word line using a first leakage current that flows between an unselected bit line and the unselected word line, to couple the selected word line and the unselected word line to the sensing circuit, and to compare a voltage level of the selected word line with the voltage level of the unselected word line.
    Type: Grant
    Filed: October 23, 2019
    Date of Patent: November 17, 2020
    Assignee: SK hynix Inc.
    Inventors: Hyung Dong Lee, Tae Hoon Kim
  • Publication number: 20200350009
    Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a bit line, a word line crossing the bit line, and a memory cell coupled to and disposed between the bit line and the word line. In a read operation, when the word line, which is in a precharged state, is floated, the bit line is driven to increase a voltage level of the bit line, and stopped when the memory cell is turned on.
    Type: Application
    Filed: October 30, 2019
    Publication date: November 5, 2020
    Inventors: Hyung Dong LEE, Tae Hoon KIM