Patents by Inventor Hyung Dong Lee

Hyung Dong Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230031695
    Abstract: A display device includes a display panel including pixels connected to scan lines and data lines, and connection line connected to the scan lines, and a scan driver which drives scan lines. The scan driver includes a scan signal output circuit which outputs a first output signal as a scan signal to a first output line and outputs a second output signal to a second output line, a signal distribution circuit which outputs the first output signal to a first or third connection line and outputs the second output signal to a second or fourth connection line in response to first and second distribution control signals, and a scan-off circuit which outputs gate-off level to at least one of the scan lines in response to first and second scan-off control signals.
    Type: Application
    Filed: February 15, 2022
    Publication date: February 2, 2023
    Inventors: Hyung Gun MA, Ji Woong KIM, Jun Yong SONG, Seong Joo LEE, Keum Dong JUNG, Sang Hyun HEO
  • Publication number: 20230019860
    Abstract: A semiconductor device including a substrate; first and second active patterns on the substrate, extending in a first direction and spaced apart in a second direction; gate electrodes on the first and second active patterns and extending in the second direction; a first gate separation structure between the first and second active patterns, extending in the first direction, and separating the gate electrodes; and a first element separation structure between the gate electrodes, extending in the second direction, and separating the second active pattern, wherein a distance to a first side of a first portion of the first gate separation structure is smaller than a distance to the first side of a second portion of the first gate separation structure, and a distance to the second side of the first portion is smaller than a distance from the second active pattern to the second side of the second portion.
    Type: Application
    Filed: April 12, 2022
    Publication date: January 19, 2023
    Inventors: Myung-Dong KO, Keon Yong CHEON, Dong Won KIM, Hyun Suk KIM, Sang Hyeon LEE, Hyung Suk LEE
  • Patent number: 11557729
    Abstract: Provided are an organic electronic element and an electronic device thereof, the organic electronic element being capable of achieving high light-emitting efficiency and a low driving voltage, and can also greatly improve the lifespan of the element by using a compound of the present invention as a phosphorescent host material.
    Type: Grant
    Filed: July 4, 2017
    Date of Patent: January 17, 2023
    Assignee: DUK SAN NEOLUX CO., LTD.
    Inventors: Soung Yun Mun, Min Ji Jo, Sun Hee Lee, Nam Geol Lee, Hyung Dong Lee
  • Patent number: 11527575
    Abstract: A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.
    Type: Grant
    Filed: April 20, 2020
    Date of Patent: December 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung Dong Lee
  • Patent number: 11527727
    Abstract: Provided are a compound capable of improving the luminous efficiency, stability and lifespan of a device employing the same, an organic electronic element employing the same, and an electronic device thereof.
    Type: Grant
    Filed: July 1, 2022
    Date of Patent: December 13, 2022
    Assignee: DUK SAN NEOLUX CO., LTD.
    Inventors: Bu Yong Yun, Hyung Dong Lee, Ki Ho So, Sun-Hee Lee, Yun Suk Lee, Zhaoyang Zhong
  • Publication number: 20220367567
    Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
    Type: Application
    Filed: August 1, 2022
    Publication date: November 17, 2022
    Inventors: Si Jung YOO, Tae Hoon KIM, Hyung Dong LEE
  • Publication number: 20220352475
    Abstract: Provided are a compound capable of improving the luminous efficiency, stability and lifespan of a device employing the same, an organic electronic element employing the same, and an electronic device thereof.
    Type: Application
    Filed: July 1, 2022
    Publication date: November 3, 2022
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Bu Yong YUN, Hyung Dong LEE, Ki Ho SO, Sun-Hee LEE, Yun Suk LEE, Zhaoyang ZHONG
  • Patent number: 11482283
    Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: October 25, 2022
    Assignee: SK hynix Inc.
    Inventors: Ki Won Lee, Seok Man Hong, Tae Hoon Kim, Hyung Dong Lee
  • Patent number: 11450808
    Abstract: Provided are a compound represented by Formula 1 or Formula A, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and an electronic device thereof, wherein the compound represented by Formula 1 or Formula A is included in the organic material layer, and thereby the driving voltage of the organic electronic device can be lowered, and the luminous efficiency and life time of the organic electronic device can be improved.
    Type: Grant
    Filed: August 20, 2018
    Date of Patent: September 20, 2022
    Assignee: DUK SAN NEOLUX CO., LTD.
    Inventors: Mi Young Chae, Hye Min Cho, Min Ji Jo, Soung Yun Mun, Sun Hee Lee, Nam Geol Lee, Hyung Dong Lee, Dae Hwan Oh, Ga Eun Lee, Sang Yong Park
  • Patent number: 11443172
    Abstract: A synapse array of a neuromorphic device is provided. The synapse array may include a pre-synaptic neuron; a row line extending from the pre-synaptic neuron in a row direction; a post synaptic neuron; a column line extending from the post-synaptic neuron in a column direction; and a synapse disposed at an intersection region between the row line and the column line. The synapse may include an n-type ferroelectric field effect transistor (n-FeFET) having a source electrode, a gate electrode and a body; a p-type ferroelectric field effect transistor (p-FeFET) having a source electrode, a gate electrode and a body; and a resistive element having a first node electrically connected to the source electrode of the n-FeFET and electrically connected to the source electrode of the p-FeFET, and the n-FeFET and the p-FeFET are electrically connected in series.
    Type: Grant
    Filed: November 13, 2017
    Date of Patent: September 13, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Patent number: 11437437
    Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: September 6, 2022
    Assignee: SK hynix Inc.
    Inventors: Si Jung Yoo, Tae Hoon Kim, Hyung Dong Lee
  • Publication number: 20220278284
    Abstract: Provided herein are an organic electronic compound capable of improving luminous efficiency, stability and lifespan of an electronic device, an organic electronic element employing the same, and an electronic device thereof.
    Type: Application
    Filed: December 3, 2021
    Publication date: September 1, 2022
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Ki Ho SO, Sang Don CHOI, Sun Hee LEE, Won Sam KIM, Soung Yun MUN, Jung Wook LEE, Hyung Dong LEE
  • Publication number: 20220278285
    Abstract: Provided are a compound represented by Formula 24, an organic electric element comprising a first electrode, a second electrode, and an organic material layer formed between the first electrode and the second electrode and comprising the compound of Formula 24, and an electronic device thereof, the element and device having improved driving voltage, luminous efficiency and life time from the employment of the compound.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 1, 2022
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Mi Young CHAE, Hye Min CHO, Min Ji JO, Soung Yun MUN, Sun Hee LEE, Nam Geol LEE, Hyung Dong LEE, Dae Hwan OH, Ga Eun LEE, Sang Yong PARK
  • Publication number: 20220220377
    Abstract: Provided are a quantum dot, a method of manufacturing the quantum dot, and an electronic device including the quantum dot. The quantum dot includes a core including a first semiconductor nanocrystal and a doping metal. The first semiconductor nanocrystal includes a group II element, a group III element, and a group V element. The quantum dot has a narrower full width at half maximum (FWHM) and superior quantum efficiency, and manufactured in a simple manner.
    Type: Application
    Filed: January 11, 2022
    Publication date: July 14, 2022
    Inventors: Do Eon KIM, Jong Moon SHIN, Chang Min LEE, Hyung Dong LEE
  • Publication number: 20220199911
    Abstract: Provided are an organic electric element including an anode, a cathode, and an organic material layer formed between the anode and the cathode, and electronic device thereof, and by including the compounds of Formulas 1 and 2 in the organic material layer, the driving voltage of the organic electric element can be lowered, and the luminous efficiency and life time of the organic electric element can be improved.
    Type: Application
    Filed: May 14, 2020
    Publication date: June 23, 2022
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Sun Hee LEE, Hyung Dong LEE, Soung Yun MUN, Jung Wook LEE
  • Patent number: 11341403
    Abstract: A synapse system of a neuromorphic device may include a pre-synaptic neuron; a pre-synaptic line extending from the pre-synaptic neuron in a first direction; a post-synaptic neuron; a post-synaptic line extending from the post-synaptic line in a second direction; a selecting controller; a selecting line extending from the selecting controller in a third direction; and a synapse electrically connected with the pre-synaptic line, the post-synaptic line, and the selecting line.
    Type: Grant
    Filed: November 2, 2017
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Hyung-Dong Lee
  • Publication number: 20220102643
    Abstract: Provides are a compound capable of improving the luminous efficiency, stability and lifespan of a device, an organic electronic element employing the same, and an electronic device thereof.
    Type: Application
    Filed: July 15, 2021
    Publication date: March 31, 2022
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Dong Hee SHIN, Hyung Dong LEE, Sun Hee LEE, Dae Sic KIM, Soung Yun MUN, Young Hoon KANG
  • Publication number: 20220056050
    Abstract: Provided is a novel compound capable of improving the luminous efficiency and stability of a device, an organic electronic element using the same, and an electronic device thereof.
    Type: Application
    Filed: August 16, 2021
    Publication date: February 24, 2022
    Applicant: DUK SAN NEOLUX CO., LTD.
    Inventors: Soung Yun MUN, Hyung Dong LEE, Sun Hee LEE, Hyoung Keun PARK, Dae Sic KIM, Byoung Yeop KANG
  • Publication number: 20220058470
    Abstract: A synapse array of a neuromorphic device comprises a first input neuron, a second input neuron, an output neuron, and a synapse. The synapse comprises a plurality of pairs of ferroelectric field effect transistors electrically connected to each other in parallel, each of the plurality of pairs of ferroelectric field effect transistors comprises a first ferroelectric field effect transistor and a second ferroelectric field effect transistor, and the first ferroelectric field effect transistor and the second ferroelectric field effect transistor are electrically connected to each other in series.
    Type: Application
    Filed: November 4, 2021
    Publication date: February 24, 2022
    Inventor: Hyung-Dong LEE
  • Patent number: 11257801
    Abstract: A stacked semiconductor package includes a first semiconductor chip having a first active surface over which first bonding pads including peripheral bonding pads and central bonding pads are arranged, a first encapsulation member, two second semiconductor chips having second active surfaces over which second bonding pads are arranged at one side peripheries and disposed to be separated from each other such that the second active surfaces face the first active surface and the second bonding pads overlap with the peripheral bonding pads, first coupling members interposed between the peripheral bonding pads and the second bonding pads, a second encapsulation member formed over second side surfaces of the second semiconductor chips including a region between the second semiconductor chips, and a mold via formed through a portion of the second encapsulation member in the region between the second semiconductor chips and coupled with the central bonding pads.
    Type: Grant
    Filed: August 1, 2019
    Date of Patent: February 22, 2022
    Assignee: SK hynix Inc.
    Inventors: Sang-Eun Lee, Hyung-Dong Lee, Eun Ko