Patents by Inventor Hyung Han

Hyung Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6924234
    Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: August 2, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ja-Hyung Han, Sang-Rok Hah, Hong-Seong Son, Duk-Ho Hong, Byung-Lyul Park
  • Patent number: 6913972
    Abstract: A method for fabricating a non-volatile memory device is provided.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: July 5, 2005
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ja-hyung Han, Myung-sik Han, Kyung-hyun Kim, Chang-ki Hong
  • Publication number: 20050066145
    Abstract: An apparatus and method for managing a memory of a computer and controlling a booting operation of the computer, are provided. The computer includes a memory having a user area and a protected security area (PSA). The user area has a management area. The method includes assigning a first partition to the user area of the memory; storing first partition information in the management area of the user area, the first partition information pertaining to the first partition; assigning a second partition to the PSA in response to an access signal, the access signal authorizing access to the PSA; storing, in the management area, second partition information pertaining to the second partition; storing the second partition information in the PSA; and removing the second partition information from the management area after storing the second partition information in the PSA.
    Type: Application
    Filed: August 9, 2004
    Publication date: March 24, 2005
    Applicant: LG Electronics Inc.
    Inventors: Hyung Han, Byung Kim, Jae Han, Do Rha
  • Publication number: 20040137829
    Abstract: Polishing apparatus and related methods employ aligned first and second magnetic field sources to adjust the compressive force and/or pressure applied by a carrier head against a target workpiece (such as a wafer) by selectively and controllably generating a repellant or attractive force between the two magnetic field sources.
    Type: Application
    Filed: November 17, 2003
    Publication date: July 15, 2004
    Inventors: Moo-Yong Park, Sang-Rok Hah, Jong-Gyoon Kim, Hong-Seong Son, Ja-Hyung Han
  • Publication number: 20040058856
    Abstract: This invention relates to delivery of biologically active organic molecules e.g. peptides or proteins into the cytoplasm. In this invention, transducing domain which is covalently attached to organic molecules is oligolysine which comprise 3-12 lysine residues. The oligolysine transducing domain-binding fusion protein is efficiently transducible into cytoplasm, and biologically active.
    Type: Application
    Filed: September 4, 2003
    Publication date: March 25, 2004
    Inventors: Soo-Young Choi, Jinseu Park, Hyeok-Yil Kwon, Jung-Hoon Kang, Tae-Chun Kang, Moo-Ho Won, Kyu-Hyung Han, Kil-Soo Lee
  • Patent number: 6596581
    Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.
    Type: Grant
    Filed: July 17, 2002
    Date of Patent: July 22, 2003
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Byung-lyul Park, Ju-hyuk Chung, Ja-hyung Han
  • Publication number: 20030064587
    Abstract: In a method and apparatus for polishing a Cu metal layer and a method for forming Cu metal wiring, Cu oxide created by a surface oxidation of a Cu metal layer is removed from the wafer. The Cu metal layer, in which Cu oxide is removed, is polished. By polishing the Cu metal layer using the above method, process failures, such as scratches, caused by the presence of remnants of Cu oxide during subsequent polishing can be prevented.
    Type: Application
    Filed: September 3, 2002
    Publication date: April 3, 2003
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ja-Hyung Han, Sang-Rok Hah, Hong-Seong Son, Duk-Ho Hong, Byung-Lyul Park
  • Publication number: 20030027385
    Abstract: A method for manufacturing a semiconductor device having a metal-insulator-metal (MIM) capacitor and a damascene wiring layer structure, wherein first and second metal wiring layers are formed in a lower dielectric layer on a semiconductor substrate such that top surfaces of the first and second metal wiring layers and the lower dielectric layer are level. First and second dielectric layers are sequentially formed to have a hole exposing the top surface of the second metal wiring layer. An upper electrode of a capacitor is formed in the hole region such that the top surfaces of the upper electrode and the second dielectric layer are level. Third and fourth dielectric layers are sequentially formed on the substrate. A damascene structure is formed to contact the top surface of the first metal wiring layer, and a contact plug is formed to contact the top surface of the upper electrode.
    Type: Application
    Filed: July 17, 2002
    Publication date: February 6, 2003
    Inventors: Byung-lyul Park, Ju-hyuk Chung, Ja-hyung Han
  • Publication number: 20030017693
    Abstract: A method of manufacturing a semiconductor device for protecting a Cu layer from post chemical mechanical polishing (CMP) corrosion and CMP equipment therefore wherein, when wafers on which a Cu layer is formed wait to be transferred to a cleaning system after being polished in a CMP equipment, the wafers collected at a stand-by station are supplied with a solution containing a corrosion inhibitor, thus at least keeping the polished surface of Cu layer wet with the solution. Then, the wafers collected at the stand-by station are transferred to the cleaning system and cleaned. In the present invention, the solution uses a solution in which the corrosion inhibitor is added to de-ionized water. Furthermore, while transferring the wafers, the surfaces of the transferred wafers are kept wet with a solution containing a corrosion inhibitor.
    Type: Application
    Filed: September 20, 2002
    Publication date: January 23, 2003
    Applicant: SAMSUNG ELECTRONICS CO., LTD.,
    Inventor: Ja-Hyung Han
  • Patent number: 6475914
    Abstract: A method of manufacturing a semiconductor device for protecting a Cu layer from post chemical mechanical polishing (CMP) corrosion and CMP equipment therefore wherein, when wafers on which a Cu layer is formed wait to be transferred to a cleaning system after being polished in a CMP equipment, the wafers collected at a stand-by station are supplied with a solution containing a corrosion inhibitor, thus at least keeping the polished surface of Cu layer wet with the solution. Then, the wafers collected at the stand-by station are transferred to the cleaning system and cleaned. In the present invention, the solution uses a solution in which the corrosion inhibitor is added to de-ionized water. Furthermore, while transferring the wafers, the surfaces of the transferred wafers are kept wet with a solution containing a corrosion inhibitor.
    Type: Grant
    Filed: July 6, 2001
    Date of Patent: November 5, 2002
    Assignee: Samsung Electronics Co., Ltd.
    Inventor: Ja-Hyung Han
  • Publication number: 20020081796
    Abstract: A method for fabricating a non-volatile memory device is provided.
    Type: Application
    Filed: August 10, 2001
    Publication date: June 27, 2002
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ja-Hyung Han, Myung-Sik Han, Kyung-Hyun Kim, Chang-Ki Hong
  • Publication number: 20020062437
    Abstract: Disclosed are a computer including a basic input output system (BIOS) memory in which a BIOS for testing and controlling each component of the computer system at the time when power is supplied to the system and a control method thereof. The computer includes an sound command signal unit provided in the BIOS memory, generating a sound command signal according to a system state of the computer, a booting sound memory in which sound data is stored, and a booting sound controller for outputting the sound data in the booting sound memory to a speaker according to the sound command signal. Accordingly, even though a sound drive is not installed in the system, the computer can output a sound and a message in order to indicate the state of the computer, such as an initial booting, termination of a system and release of a power saving mode.
    Type: Application
    Filed: May 31, 2001
    Publication date: May 23, 2002
    Inventors: Seung-Gi Shin, Hyung-Han Lee
  • Publication number: 20020034876
    Abstract: A method of manufacturing a semiconductor device for protecting a Cu layer from post chemical mechanical polishing (CMP) corrosion and CMP equipment therefore wherein, when wafers on which a Cu layer is formed wait to be transferred to a cleaning system after being polished in a CMP equipment, the wafers collected at a stand-by station are supplied with a solution containing a corrosion inhibitor, thus at least keeping the polished surface of Cu layer wet with the solution. Then, the wafers collected at the stand-by station are transferred to the cleaning system and cleaned. In the present invention, the solution uses a solution in which the corrosion inhibitor is added to de-ionized water. Furthermore, while transferring the wafers, the surfaces of the transferred wafers are kept wet with a solution containing a corrosion inhibitor.
    Type: Application
    Filed: July 6, 2001
    Publication date: March 21, 2002
    Inventor: Ja-Hyung Han
  • Patent number: 6320148
    Abstract: A method of separating particulate materials of different properties has been developed. It consists of feeding a mixture of dry, powdered materials to one end of the surface of a planar electrode, which is vibrating to move the particles forward. At least one type of the particulate materials acquires a charge via conduction or triboelectrification. Those particles that acquire charges of the same sign as that of the planar electrode are lifted and collected at the V-shaped counter electrodes installed above. The new separation method is particularly useful for removing unburned carbons from fly ash and any other conducting materials from nonconducting ones.
    Type: Grant
    Filed: August 5, 1999
    Date of Patent: November 20, 2001
    Inventors: Roe-Hoan Yoon, Oh-Hyung Han, Eric S. Yan, Byung-Wook Park
  • Patent number: 6259265
    Abstract: A unified test system for testing the performance of a printed circuit board assembly, and a test method using the same. A masking board and a printed circuit board assembly are loaded onto a pin board from which test process connection pins having different height project. The test process connection pins, a power input connector and a signal interface connector are connected with the printed circuit board assembly and pins installed on the printed circuit board assembly. Thereafter, in-circuit-test signals are generated to test the printed circuit board assembly. Only function-circuit-test connection pins among the test process connection pins are connected with the printed circuit board assembly, and functions between the printed circuit board assembly and a head disk assembly are tested. Finally, results of the in-circuit-test process and the function-circuit-test process are displayed.
    Type: Grant
    Filed: October 13, 1999
    Date of Patent: July 10, 2001
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Jong-Hyung Han, Yong-Taek Sim, Tae-Young Kwak
  • Patent number: 5815409
    Abstract: A control system for an automatic shutdown of a power supply constructed with a switching mode power supply (SMPS) receiving an AC voltage and converting the AC voltage into a DC voltage; a main board receiving the DC voltage output from the switching mode power supply; and a control circuit controlling and maintaining the supply of power from the switching mode power supply to the main board until a shutdown process is performed when power is turned OFF, wherein the control system enables the automatic shutdown of a power supply while preventing a file or a system from being damaged by automatically cutting off power after performing the shutdown process by the power control system even though the power switch is turned OFF due to the carelessness of the user or an external factor.
    Type: Grant
    Filed: October 29, 1996
    Date of Patent: September 29, 1998
    Assignee: SamSung Electronics Co., Ltd.
    Inventors: Hyung-Han Lee, Jee-kyoung Park, Yong-Seok Shin