Patents by Inventor Hyung Hwan An

Hyung Hwan An has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8786047
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Grant
    Filed: July 9, 2012
    Date of Patent: July 22, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Bong-Ho Choi, Jin-Yul Lee, Seung-Seok Pyo
  • Publication number: 20140179118
    Abstract: A surface treatment method for a semiconductor device includes providing a substrate where a plurality of projected patterns are formed, forming a hydrophobic coating layer on a surface of each of the plurality of projected patterns, rinsing the substrate with deionized water, and drying the substrate, wherein the hydrophobic coating layer is formed using a coating agent that includes phosphate having more than one hydrocarbon group, phosphonate having more than one hydrocarbon group, or a mixture thereof.
    Type: Application
    Filed: March 15, 2013
    Publication date: June 26, 2014
    Applicant: SK hynix Inc.
    Inventors: Sung-Hyuk CHO, Hyo-Sang KANG, Sung-Ki PARK, Kwon HONG, Hyung-Soon PARK, Hyung-Hwan KIM, Young-Bang LEE, Ji-Hye HAN, Tae-Yeon JUNG, Hyeong-Jin NOR
  • Patent number: 8697525
    Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: April 15, 2014
    Assignee: SK Hynix Inc.
    Inventors: Hyung-Hwan Kim, Seong-Su Lim, Sung-Eun Park, Seung-Seok Pyo, Min-Cheol Kang
  • Publication number: 20140057458
    Abstract: A method for forming a silicon oxide film of a semiconductor device is disclosed. The method of forming the silicon oxide film of the semiconductor device includes performing surface processing using an amine-based compound, so that the uniformity and density of the silicon oxide film may be improved.
    Type: Application
    Filed: March 15, 2013
    Publication date: February 27, 2014
    Applicant: SK HYNIX INC.
    Inventors: Hyung Soon PARK, Kwon HONG, Jong Min LEE, Hyung Hwan KIM, Ji Hye HAN, Geun Su LEE
  • Publication number: 20140007933
    Abstract: Disclosed are a thin film solar cell and a method of manufacturing the thin film solar cell. The thin film solar cell according to an exemplary embodiment of the present invention thin film solar cell includes a substrate: a front electrode layer formed on the substrate; an oxide layer formed on the front electrode layer: a light absorbing layer (intrinsic layer) formed on the oxide layer; and a back electrode layer formed on the light absorbing layer, wherein the oxide layer is formed of a material selected from MoO2, WO2, V2O5, NiO and CrO3.
    Type: Application
    Filed: August 10, 2012
    Publication date: January 9, 2014
    Applicant: KOREA INSTITUTE OF MACHINERY & MATERIALS
    Inventors: Seoung Yoon RYU, Dong Ho KIM, Kee Seok NAM, Yong Soo JEONG, Jung Dae KWON, Sung Hun LEE, Jung Heum YUN, Gun Hwan LEE, Hyung Hwan JUNG, Sung Gyu PARK, Chang Su KIM, Jae Wook KANG, Keong Su LIM, Sang II PARK
  • Publication number: 20140011314
    Abstract: Disclosed are a thin film solar cell and a method of manufacturing the thin film solar cell. The thin film solar cell according to an exemplary embodiment of the present invention thin film solar cell includes a substrate: a front electrode layer formed on the substrate; an oxide layer formed on the front electrode layer: a light absorbing layer (intrinsic layer) formed on the oxide layer; and a back electrode layer formed on the light absorbing layer, wherein the oxide layer is formed of a material selected from MoO3, WO3, V2O5, NiO and CrO3.
    Type: Application
    Filed: August 9, 2013
    Publication date: January 9, 2014
    Applicant: Korea Institute of Machinery & Materials
    Inventors: Seoung Yoon Ryu, Dong Ho Kim, Kee Seok Nam, Yong Soo Jeong, Jung Dae Kwon, Sung Hun Lee, Jung Heum Yun, Gun Hwan Lee, Hyung Hwan Jung, Sung Gyu Park, Chang Su Kim, Jae Wook Kang, Koeng Su Lim, Sang Il Park
  • Publication number: 20130249048
    Abstract: A semiconductor device with an isolation layer buried in a trench includes an interface layer formed on the surface of the trench, a buffer layer formed in the interface layer at a bottom corner of the trench, a liner layer formed over the interface layer, and a gap-fill layer gap-filling the trench over the liner layer. The trench includes a micro-trench formed at the bottom corner thereof, and the buffer layer fills the micro-trench.
    Type: Application
    Filed: July 9, 2012
    Publication date: September 26, 2013
    Inventors: Hyung-Hwan KIM, Bong-Ho CHOI, Jin-Yul LEE, Seung-Seok PYO
  • Patent number: 8384188
    Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.
    Type: Grant
    Filed: May 14, 2012
    Date of Patent: February 26, 2013
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung-Hwan Kim
  • Publication number: 20120223408
    Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.
    Type: Application
    Filed: May 14, 2012
    Publication date: September 6, 2012
    Inventor: Hyung-Hwan KIM
  • Publication number: 20120168899
    Abstract: A semiconductor device includes a plurality of first conductive patterns separated by a damascene pattern, a second conductive pattern buried in the damascene pattern, and a spacer including an air gap between the second conductive pattern and the first conductive patterns.
    Type: Application
    Filed: May 5, 2011
    Publication date: July 5, 2012
    Inventors: Hyung-Hwan KIM, Seong-Su Lim, Sung-Eun Park, Seung-Seok Pyo, Min-Cheol Kang
  • Patent number: 8198171
    Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: June 12, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung-Hwan Kim
  • Publication number: 20120144408
    Abstract: Provided is an apparatus and method for generating digital content. The apparatus includes a physical information manager configured to manage information about a physical item distributed off-line, a video production manager configured to produce video content by generating and converting a video image of the physical item, and an interactive video production manager configured to generate digital content capable of providing an interactive service by applying a service interaction element to the video produced to be served on-line. Also, the apparatus further includes an intellectual property right manager configured to register and manage the copyright and intellectual property right related to the generated digital content and permit use of the copyright and the intellectual property right, and a unique number manager configured to issue a unique number so that the generated digital content can be identified in a distribution process.
    Type: Application
    Filed: November 14, 2011
    Publication date: June 7, 2012
    Applicant: Electronics and Telecommunications Research Institute
    Inventors: Hyung Hwan KIM, Sung Jin HUR
  • Patent number: 8187969
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer on a surface including the contact holes; forming contact plugs in such a way as to be isolated in the respective contact holes, by etching a surface of the first conductive layer to expose upper end surfaces of the conductive patterns; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming an insulation layer on the resultant structure.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: May 29, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventor: Hyung Hwan Kim
  • Publication number: 20110101488
    Abstract: A method for fabricating a semiconductor device includes: providing a substrate; forming a plurality of trenches by etching the substrate; forming a first isolation layer by filling the plurality of the trenches with a first insulation layer; recessing the first insulation layer filling a first group of the plurality of the trenches to a predetermined depth; forming a liner layer over the first group of the trenches with the first insulation layer recessed to the predetermined depth; and forming a second isolation layer by filling the first group of the trenches, where the liner layer is formed, with a second insulation layer.
    Type: Application
    Filed: December 17, 2009
    Publication date: May 5, 2011
    Inventor: Hyung-Hwan Kim
  • Publication number: 20100330792
    Abstract: A method for manufacturing a semiconductor device includes the steps of forming conductive patterns on a substrate; forming an interlayer dielectric between the conductive patterns; defining contact holes in the interlayer dielectric to expose portions of the substrate between the conductive patterns; forming a first conductive layer on a surface including the contact holes; forming contact plugs in such a way as to be isolated in the respective contact holes, by etching a surface of the first conductive layer to expose upper end surfaces of the conductive patterns; etching a partial thickness of the conductive patterns so that the upper end surfaces of the conductive patterns are lower than an upper end surface of the interlayer dielectric; and forming an insulation layer on the resultant structure.
    Type: Application
    Filed: December 18, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventor: Hyung Hwan KIM
  • Patent number: 7855109
    Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is
    Type: Grant
    Filed: December 30, 2008
    Date of Patent: December 21, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Hyung Hwan Kim, Kwang Kee Chae, Jong Goo Jung, Ok Min Moon, Young Bang Lee, Sung Eun Park
  • Publication number: 20100159683
    Abstract: A method for fabricating a semiconductor device having a recess channel includes forming an isolation layer that delimits an active region over a semiconductor substrate; exposing a region to be formed with a bulb recess trench over the semiconductor substrate; forming an upper trench by etching the exposed portion of the semiconductor substrate; forming, on a side wall of the upper trench, a silicon nitride barrier layer that exposes a bottom face of the upper trench but blocks a side wall of the upper trench; forming a lower trench of a bulb type by etching the exposed bottom face of the upper trench using the etch barrier layer as an etch mask, to form the bulb recess trench including the upper trench and the lower trench; forming a fin-structured bottom protrusion part including an upper face and a side face by etching the isolation layer so that the isolation layer has a surface lower than the bottom face of the lower trench; and forming a gate stack overlapped with the bulb recess trench and the bottom
    Type: Application
    Filed: June 29, 2009
    Publication date: June 24, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Jin Yul Lee, Bong Ho Choi, Kwang Kee Chae, Dong Seok Kim, Jae Seon Yu, Hyung Hwan Kim, Jae Kyun Lee
  • Publication number: 20100151656
    Abstract: A method for manufacturing a semiconductor device according to the present invention, comprising the steps of: forming a screen oxide layer over the surface of an active region of a semiconductor substrate in which an isolation structure defining the active region is formed; forming a first recess pattern in the active region and a second recess pattern in the isolation structure by etching a gate forming area in the active region and the isolation structure part extended thereto; removing the screen oxide film and simultaneously expanding the width of the second recess pattern; forming a first insulation dielectric layer over the resultant of the substrate having the second recess pattern with the expanded width so that the first insulation dielectric layer is blocked at the upper end thereof in the first recess pattern and it is deposited along the profile in the second recess pattern; forming a second insulation dielectric layer over the first insulation dielectric layer so that the second recess patter is
    Type: Application
    Filed: December 30, 2008
    Publication date: June 17, 2010
    Inventors: Hyung Hwan KIM, Kwang Kee CHAE, Jong Goo JUNG, Ok Min MOON, Young Bang LEE, Sung Eun PARK
  • Patent number: 7715317
    Abstract: Provided is a flow generation method for Internet traffic measurement. In the flow generation method, dependency between packet collecting time and flow generating time is removed using a virtual timer and a flow generation completion processing interval is controlled to skip by a unit time in response to a user's request. Also, a fragmented packet processing method is selectively used at need and a FIN timeout is applied selectively to a timeout mechanism used in flow generation completion. Thereby, this invention can improve accuracy and efficiency of Internet traffic measurement.
    Type: Grant
    Filed: September 2, 2004
    Date of Patent: May 11, 2010
    Assignee: Electronics and Telecommunications Research Institute
    Inventors: Jeong Sook Park, Seung Hyun Yoon, Hyung Hwan Kim, Chang Hoon Kim, Hyung Seok Chung, Byung Joon Lee, Taesang Choi, Tae Soo Chung
  • Publication number: 20090267199
    Abstract: An isolation layer of a semiconductor device and a process for forming the same is described herein. The isolation layer includes a trench that is defined and formed in a semiconductor substrate. A first liner nitride layer is formed on the surface of the trench and a flowable insulation layer is formed in the trench including the first liner nitride layer. The flowable insulation layer is formed such to define a recess in the trench. A second liner nitride layer is formed on the recess including the flowable insulation layer and the first liner nitride layer. Finally, an insulation layer is formed in the recess on the second liner nitride layer to completely fill the trench.
    Type: Application
    Filed: July 3, 2008
    Publication date: October 29, 2009
    Inventors: Hyung Hwan KIM, Kwang Kee CHAE, Jong Goo JUNG, Ok Min MOON, Young Bang LEE, Sung Eun PARK