Abstract: Provided is an automatic wall mounting system for a wall-mounted television (TV). The system has a support plate 110, a left/right tilting part 120, and a TV mount plate 130. The TV mount plate 130 tilting left/right about the support plate 110. The left/right tilting part 120 includes a left/right tilting motor 121 having driving shafts 121a and 121b, gear parts 122 and 123 geared and ungeared by the same length in an opposite direction, and having connection links 122a and 123a at their front ends, a first rotary shaft 124 having a connector 124a at its predetermined portion, and a second rotary shaft 125 having a connector 125a at its predetermined portion.

Abstract: Provided is an automatic wall mounting system for a wall-mounted television (TV). The system includes a fixing plate, an elevating plate, and an elevation manipulation unit. The fixing plate is fixingly mounted on a wall body and has fixing rails and sliders at its both side ends. The sliders slide on the fixing rails. The elevating plate is coupled at its both side ends to the sliders of the fixing plate, and mounts the TV in its front. The elevation manipulation unit is coupled to each of the fixing plate and the elevating plate, and elevates or descends the elevating plate about the fixing plate.

Abstract: Provided is an automatic wall mounting system for a wall-mounted television (TV). The system includes a support plate, a tilt plate, and a tilt manipulation unit. The support plate is mounted on a wall body, and has a plurality of upper and lower supports. The tilt plate has joints coupled to the lower supports of the support plate, and has a joint provided at an upper end. The tilt manipulation unit is provided between the support plate and the tilt plate, and tilts up/down an upper end of the tilt plate about the support plate.

Abstract: Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.

Abstract: A method for forming a storage node contact plug in a semiconductor device is provided. The method includes: forming an inter-layer insulation layer over a substrate having a conductive plug; etching a portion of the inter-layer insulation layer using at least line type storage node contact masks as an etch mask to form a first contact hole with sloping sidewalls; etching another portion of the inter-layer insulation layer underneath the first contact hole to form a second contact hole exposing the conductive plug, the second contact hole having substantially vertical sidewalls; and filling the first and second storage node contact holes to form a storage node contact plug.

Abstract: A method for forming a contact of a semiconductor deices is disclosed. More specifically, in the method for forming a contact of a semiconductor device, an interlayer dielectric (hereinafter, referred to as “ILD”) layer is polished using a CMP slurry having high selectivity to an oxide film in a STI (shallow trench isolation) etching process for forming a line-type storage node contact (hereinafter, referred to as “SNC”, and an ILD layer having a predetermined thickness is re-formed on the semiconductor substrate to secure a sufficient etching margin to a subsequent etching process, thereby preventing loss of a hard mask nitride film of a bit line and reducing fail of a self-aligned contact (hereinafter, referred to as “SAC”) between a storage node and a bit line.

Abstract: The present invention discloses method for manufacturing alignment mark wherein a predetermined thickness of a device isolation film is etched prior to removing a pad nitride film during a shallow trench isolation process to increase contrast. In accordance with the method, a pad nitride film pattern and a pad oxide film pattern exposing a predetermined portion of the semiconductor substrate are formed. The semiconductor substrate is etched using the pad nitride film pattern as a mask to form an alignment mark trench. A device isolation film is formed in the trench and a predetermined thickness of the device isolation film is etched to form an alignment mark. The pad nitride film pattern is then removed.

Abstract: A method of forming a gate in a semiconductor device includes forming a dummy gate insulating layer on a semiconductor substrate having a field oxide layer isolating the device, depositing a dummy gate polysilicon layer and a hard mask layer on the dummy gate insulating layer sequentially, patterning the hard mask layer into a mask pattern and patterning the dummy gate polysilicon layer using the mask pattern as an etch barrier, forming spacers at both sidewalls of the dummy gate polysilicon layer, depositing an insulating interlayer on the resultant structure after forming the spacers, exposing a surface of the dummy gate polysilicon layer by carrying out an oxide layer CMP process having a high selection ratio against the dummy gate polysilicon layer, forming a damascene structure by removing the dummy gate polysilicon layer and the dummy gate insulating layer using the insulating interlayer as another etch barrier, depositing a gate insulating layer and a gate metal layer on the entire surface of the semic

Abstract: Disclosed is a method for forming landing plug contacts in a semiconductor device. The method includes the steps of: forming a plurality of gate structures on a substrate, each gate structure including a gate hard mask; forming an inter-layer insulation layer on the gate structures; planarizing the inter-layer insulation layer through a chemical mechanical polishing (CMP) process until the gate hard mask is exposed; forming a hard mask material on the planarized inter-layer insulation layer; patterning the hard mask material, thereby forming a hard mask; forming a plurality of contact holes exposing the substrate disposed between the gate structures by etching the planarized inter-layer insulation layer with use of the hard mask as an etch mask; forming a polysilicon layer on the contact holes; and forming the landing plug contacts buried into the contact holes through a planarization process performed to the polysilicon layer until the gate hard mask is exposed.

Abstract: The present invention discloses method for manufacturing alignment mark wherein a predetermined thickness of a device isolation film is etched prior to removing a pad nitride film during a shallow trench isolation process to increase contrast. In accordance with the method, a pad nitride film pattern and a pad oxide film pattern exposing a predetermined portion of the semiconductor substrate are formed. The semiconductor substrate is etched using the pad nitride film pattern as a mask to form an alignment mark trench. A device isolation film is formed in the trench and a predetermined thickness of the device isolation film is etched to form an alignment mark. The pad nitride film pattern is then removed.

Abstract: A Chemical Mechanical Polishing(abbreviated as “CMP”) slurry composition for polysilicon and method of forming a self-aligned floating gate of a flash memory device are disclosed for performing CMP process using slurry having higher polishing selectivity to polysilicon than to isolation oxide film which is an etching barrier film.

Abstract: A nitride CMP slurry having selectivity to nitride over oxide. The slurry increases the polishing speed of a nitride film by varying the pH of the slurry, and polishes the nitride film faster than an oxide film by decreasing the polishing speed of the oxide film. As a result, the slurry provides a CMP process for manufacturing a high density and highly integrated semiconductor device and a structural development of new concept device.

Abstract: The present invention relates to extract and fraction of cacao bean and cacao bean husk, which inhibit the suppression of GJIC (gap junctional intercellular communication) and inhibit DNA synthesis of cancer cell, pathological phenomena occurring during promotion and progression stages of carcinogenesis.

Abstract: Disclosed is theobromine with an anti-carcinogenic activity which inhibits the suppression of GJIC (gap junctional intercellular communication), a pathological phenomenon occurring during development of various kinds of cancers including liver cancer, as well as DNA synthesis of cancer cells thereby inhibiting proliferation of liver, gastric and colon cancer cells.

Abstract: A chemical mechanical polishing(abbreviated as “CMP”) slurry composition for oxide films, and a method of forming a self-aligned floating gate of a flash memory device are disclosed for performing a CMP process using slurry having higher polishing selectivity to an oxide film than to a nitride film which is an etching barrier film.

Abstract: Method of forming flash memory device is disclosed, more particularly, method of forming self-aligned floating gate by performing Chemical Mechanical Polishing (abbreviated as “CMP”) process using slurry having higher polishing selectivity to oxide films than to nitride films and slurry having higher polishing selectivity to polysilicon than to oxide films.

Abstract: The present invention relates to extract and fraction of cacao bean and cacao bean husk, which inhibit the suppression of GJIC (gap junctional intercellular communication) and inhibit DNA synthesis of cancer cell, pathological phenomena occurring during promotion and progression stages of carcinogenesis.

Abstract: Disclosed is theobromine with an anti-carcinogenic activity which inhibits the suppression of GJIC (gap junctional intercellular communication), a pathological phenomenon occurring during development of various kinds of cancers including liver cancer, as well as DNA synthesis of cancer cells thereby inhibiting proliferation of liver, gastric and colon cancer cells.

Abstract: The present Invention is to provide a novel strain, Candida magnoliae (KCCM-10252) producing mannitol isolated from the fermentation sludge collected from a xylitol manufacturing company, and further a method for manufacturing mannitol with high yield and high productivity by optimizing various culture conditions and medium composition using the new strain, Candida magnoliae.

Abstract: A nitride CMP slurry having selectivity to nitride over oxide. The slurry increases the polishing speed of a nitride film by varying the pH of the slurry, and polishes the nitride film faster than an oxide film by decreasing the polishing speed of the oxide film. As a result, the slurry provides a CMP process for manufacturing a high density and highly integrated semiconductor device and a structural development of new concept device.