Patents by Inventor Hyung Jin Jeon
Hyung Jin Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8143099Abstract: The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.Type: GrantFiled: May 5, 2009Date of Patent: March 27, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Jin Gu Kim, Jong Hwan Baek, Jong Yun Lee, Hyung Jin Jeon, Young Do Kweon
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Patent number: 8106308Abstract: A printed circuit board for a package includes a first insulation layer, on one side of which an electronic component having a plurality of electrical contacts is mounted; a plurality of first bond pads formed on the other side of the first insulation layer in predetermined intervals, which are electrically connected with the electrical contacts; a second insulation layer stacked on the other side of the first insulation layer, with those portions removed where the first bond pads are formed; and a second bond pad, which is formed on a surface of the second insulation layer in correspondence with positions between the plurality of the first bond pads, and which is electrically connected with the electrical contacts. The bond pads can be implemented in two layers, as opposed to the case of forming the bond pads in one layer, in a predetermined area of a printed circuit board.Type: GrantFiled: September 17, 2007Date of Patent: January 31, 2012Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung-Jin Jeon, Young-Hwan Shin, Tae-Gon Lee
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Publication number: 20120012378Abstract: Disclosed is a printed circuit board, including a base member, an insulating layer formed on each of both surfaces of the base member so that the surfaces of the base member are flattened, a circuit layer formed on the insulating layer, and a via for connecting the circuit layer formed on one surface of the base member with the circuit layer formed on the other surface of the base member. A method of manufacturing the printed circuit board is also provided.Type: ApplicationFiled: September 29, 2010Publication date: January 19, 2012Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Jin Jeon, Young Do Kweon, Seung Wook Park, Seon Hee Moon
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Publication number: 20110201156Abstract: A method of manufacturing a wafer level package including: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant and cutting a wafer level package along the dicing lines coated with the resin into units.Type: ApplicationFiled: April 22, 2011Publication date: August 18, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Gu Kim, Young Do Kweon, Hyung Jin Jeon, Seung Wook Park, Hee Kon Lee, Seon Hee Moon
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Patent number: 7960806Abstract: A sub-mount, a light emitting diode package, and a method of manufacturing thereof are disclosed. A sub-mount, on which multiple light emitting diodes are mounted, can include a multiple number of metal bodies on which the light emitting diodes are respectively mounted, and an oxide wall interposed between the metal bodies such that the adjacent metal bodies are supported by each other but electrically disconnected from each other. By utilizing certain embodiments of the invention, a high heat releasing effect may be obtained, and manufacturing costs may be reduced.Type: GrantFiled: October 1, 2008Date of Patent: June 14, 2011Assignee: Samsung LED Co., Ltd.Inventors: Young-Ki Lee, Seog-Moon Choi, Hyung-Jin Jeon, Sang-Hyun Shin
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Publication number: 20110129960Abstract: A method of manufacturing a stacked wafer level package includes: preparing a substrate; forming a conductive layer on the substrate; forming chip connection pads and internal connection pads on the conductive layer; forming solder balls connected to the internal connection pads; mounting a semiconductor chip on the conductive layer to be connected to the chip connection pads; forming a sealing member to seal the solder balls and the semiconductor chip; separating the substrate from the conductive layer; forming a rearrangement wiring layer by etching the conductive layer; forming an external connection on the rearrangement wiring layer; forming contact holes in the sealing member to expose the solder balls; and stacking an electronic component to be electrically connected to the solder balls exposed through the contact holes.Type: ApplicationFiled: February 9, 2011Publication date: June 2, 2011Applicant: Samsung Electro-Mechanics Co., Ltd.Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Yuan Jing Li, Jong Yun Lee
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Patent number: 7947530Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.Type: GrantFiled: May 5, 2009Date of Patent: May 24, 2011Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Jin Gu Kim, Young Do Kweon, Hyung Jin Jeon, Seung Wook Park, Hee Kon Lee, Seon Hee Moon
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Publication number: 20110062533Abstract: A device package substrate includes: a substrate having a cavity formed on a top surface thereof, the cavity having a chip mounting region; a first interconnection layer formed to extend to the inside of the cavity; a second interconnection layer formed to be spaced apart from the first interconnection layer; a chip positioned in the chip mounting region so as to be connected to the first and second interconnection layers; an insulating layer formed to cover the first and second interconnection layers and the chip and having a contact hole exposing a part of the second interconnection layer; and a bump pad formed in the contact hole so as to be connected to external elements.Type: ApplicationFiled: December 18, 2009Publication date: March 17, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Hyung Jin Jeon, Young Do Kweon
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Publication number: 20110061911Abstract: An interposer includes: an insulation plate where a via is formed, the insulation plate including a resin or a ceramic; a first upper redistribution layer electrically connected to the via along a circuit pattern designed on the top surface of the insulation plate; a first upper protection layer laminated to expose a portion of the first upper redistribution layer and protecting the first upper redistribution layer; a second upper redistribution layer electrically connected to the first upper redistribution layer and laminated along a designed circuit pattern designed; a second upper protection layer laminated to expose a portion of the second upper redistribution layer and protecting the second upper redistribution layer; and an under bump metallization (UBM) formed at the exposed portion of the second upper redistribution layer.Type: ApplicationFiled: December 17, 2009Publication date: March 17, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO. LTD.Inventors: Hyung Jin Jeon, Jong In Ryu, Seung Wan Shin, Seon Hee Moon, Young Do Kweon, Seung Wook Park
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Publication number: 20110045668Abstract: There is provided a method of manufacturing a wafer level device package, the method including: forming a conductive pad on at least one area of a substrate; forming a first insulation layer on the substrate, the first insulation layer having an opening allowing the conductive pad to be exposed; forming a wiring layer connected to the conductive pad on the first insulation layer; forming a conductive diffusion barrier layer on the wiring layer to seal the wiring layer; forming a second insulation layer on the diffusion barrier layer, the second insulation layer having a contact hole allowing a part of diffusion barrier layer to be exposed; and forming a bump pad in the contact hole. This method allows for a reduction in processing time and costs by substituting a simple electroless plating process for a complicated photolithography process in the formation of the bump pad and the diffusion barrier layer.Type: ApplicationFiled: December 17, 2009Publication date: February 24, 2011Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Jin Jeon, Young Do Kweon, Seung Wook Park, Jong Yun Lee
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Publication number: 20100159646Abstract: The present invention relates to a method of manufacturing a wafer level package including the steps of: preparing a substrate wafer including a plurality of pads formed on a bottom surface, a plurality of chips positioned on a top surface, and dicing lines for dividing the chips; forming external connection units on the pads; coating resin on the dicing lines by positioning masks on the substrate wafer to expose only the dicing lines; removing the masks; encapsulating the chips positioned between the resin by coating the chips with encapsulant; removing the resin coated on the dicing lines; and cutting a wafer level package along the dicing lines exposed by removing the resin into units.Type: ApplicationFiled: May 5, 2009Publication date: June 24, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jin Gu Kim, Young Do Kweon, Hyung Jin Jeon, Seung Wook Park, Hee Kon Lee, Seon Hee Moon
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Publication number: 20100149770Abstract: The present invention relates to a semiconductor stack package including: a printed circuit board; a first semiconductor chip mounted on the printed circuit board; a second semiconductor chip mounted on the printed circuit board in parallel with the first semiconductor chip; a first rearrangement wiring layer positioned on the first semiconductor chip; a second rearrangement wiring layer which constitutes one circuit together with the first rearrangement wiring layer and is positioned on the second semiconductor chip; and a third semiconductor chip which is electrically connected to the first and second rearrangement wiring layers and of which both ends are separately positioned on the first and second semiconductor chips.Type: ApplicationFiled: May 5, 2009Publication date: June 17, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Jin Gu Kim, Jong Hwan Baek, Jong Yun Lee, Hyung Jin Jeon, Young Do Kweon
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Publication number: 20100144152Abstract: The present invention relates to a method of manufacturing a semiconductor package capable of simplifying a process and remarkably reducing a production cost by including the steps of: preparing a different bonded panel including at least one metal layer; forming a pad unit electrically connected to the metal layer; mounting a semiconductor chip over the different bonded panel to be electrically connected to the pad unit; sealing the semiconductor chip; forming a rearrangement wiring layer by etching the metal layer; and forming an external connection unit electrically connected to the rearrangement wiring layer.Type: ApplicationFiled: May 5, 2009Publication date: June 10, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Jin Gu Kim, Jong Hwan Baek, Jong Yun Lee, Hyung Jin Jeon, Young Do Kweon
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Publication number: 20100117218Abstract: The present invention relates to a stacked wafer level package and a method of manufacturing the same. The stacked wafer level package in accordance with the present invention can improve a misalignment problem generated in a stacking process by performing a semiconductor chip mounting process, a rearrangement wiring layer forming process, the stacking process and so on after previously bonding internal connection means for interconnection between stacked electronic components to a conductive layer for forming a rearrangement wiring layer, thereby improving reliability and yield and reducing manufacturing cost.Type: ApplicationFiled: July 13, 2009Publication date: May 13, 2010Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Seung Wook Park, Young Do Kweon, Jin Gu Kim, Ju Pyo Hong, Hee Kon Lee, Hyung Jin Jeon, Jing Li Yuan, Jong Yun Lee
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Patent number: 7663250Abstract: A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.Type: GrantFiled: September 4, 2008Date of Patent: February 16, 2010Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung Jin Jeon, Sung Yi, Jong Yun Lee, Young Do Kweon, Jong Hwan Baek
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Publication number: 20090309216Abstract: A wafer level package and a manufacturing method thereof capable of reducing stress between an under bump metal and a bump. The wafer level package includes a substrate provided with a plurality of chip pads on a top surface; a first passivation layer to expose the chip pads; vias connected to the chip pads by passing through the first passivation layer; a metal wiring layer formed on the first passivation layer and connected to the vias; an under bump metal formed on the first passivation layer to be connected to the metal wiring layer and having a buffer pattern separated through a trench on a center; a second passivation layer formed on the first passivation layer to expose the under bump metal; a first bump formed on the buffer pattern; and a second bump filling the trench and formed on the first bump and the under bump metal.Type: ApplicationFiled: September 4, 2008Publication date: December 17, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Hyung Jin Jeon, Sung Yi, Jong Yun Lee, Young Do Kweon, Jong Hwan Baek
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Patent number: 7632709Abstract: A method of manufacturing a wafer level package is disclosed. The method may include stacking an insulation layer over a wafer substrate; processing a via hole in the insulation layer; forming a seed layer over the insulation layer; forming a plating resist, which is in a corresponding relationship with a redistribution pattern, over the seed layer; forming the redistribution pattern, which includes a terminal for external contact, by electroplating; and coupling a conductive ball to the terminal. As multiple redistribution layers can be formed using inexpensive PCB processes, the manufacturing costs can be reduced, and the stability and efficiency of the process can be increased.Type: GrantFiled: April 25, 2008Date of Patent: December 15, 2009Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: Hyung-Jin Jeon, Sung Yi, Young-Do Kweon, Jong-Yun Lee, Joon-Seok Kang, Seung-Wook Park
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Publication number: 20090302468Abstract: Disclosed is a printed circuit board including a semiconductor chip, which includes a semiconductor chip having a connection pad, which is exposed, on the upper surface thereof, a first solder ball formed on the connection pad and having a first melting point, a printed circuit board having an external connection terminal formed at the outermost circuit layer thereof, and a second solder ball formed on the external connection terminal, connected to the first solder ball, and having a second melting point higher than the first melting point. In the printed circuit board including a semiconductor chip, the distance between the printed circuit board and the semiconductor chip is increased, thus realizing high resistance to flexure due to the difference in thermal expansion coefficient between the printed circuit board and the semiconductor chip.Type: ApplicationFiled: September 12, 2008Publication date: December 10, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Jong Hwan Baek, Sung Yi, Young Do Kweon, Jong Yun Lee, Hyung Jin Jeon, Joon Seok Kang
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Publication number: 20090267505Abstract: The present invention relates to a light emitting device package and a method of manufacturing the same. There is provided a light emitting device package including a metal core; an insulating layer formed on the metal core; a metal layer formed on the insulating layer; a first cavity formed by removing parts of the metal layer and the insulating layer to expose a top surface of the metal core; and a light emitting device directly mounted on the top surface of the metal core in the first cavity and further there is provided a method of manufacturing the light emitting device package.Type: ApplicationFiled: June 17, 2008Publication date: October 29, 2009Inventors: Young Ki Lee, Seog Moon Choi, Hyung Jin Jeon, Sang Hyun Shin
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Publication number: 20090261356Abstract: A sub-mount, a light emitting diode package, and a method of manufacturing thereof are disclosed. A sub-mount, on which multiple light emitting diodes are mounted, can include a multiple number of metal bodies on which the light emitting diodes are respectively mounted, and an oxide wall interposed between the metal bodies such that the adjacent metal bodies are supported by each other but electrically disconnected from each other. By utilizing certain embodiments of the invention, a high heat releasing effect may be obtained, and manufacturing costs may be reduced.Type: ApplicationFiled: October 1, 2008Publication date: October 22, 2009Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Young-Ki Lee, Seog-Moon choi, Hyung-Jin Jeon, Sang-Hyun Shin