Patents by Inventor Hyung Jun Jeon
Hyung Jun Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240379639Abstract: An example semiconductor package includes a structure, a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure, a dummy semiconductor chip disposed on and contacting the upper surface of the structure, a molding layer surrounding a sidewall of the first semiconductor chip and a sidewall of the dummy semiconductor chip on the upper surface of the structure, a redistribution layer disposed on an upper surface of the first semiconductor chip, an upper surface of the dummy semiconductor chip, and an upper surface of the molding layer, a first through-via extending through the molding layer in a vertical direction and electrically connecting the structure and the redistribution layer, a second through-via extending through the dummy semiconductor chip in the vertical direction and electrically connecting the structure and the redistribution layer, and a capacitor disposed inside the dummy semiconductor chip.Type: ApplicationFiled: December 27, 2023Publication date: November 14, 2024Inventors: Myung Joo Park, Hyung Jun Jeon, Pil-Kyu Kang
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Publication number: 20240186247Abstract: A semiconductor device includes: a substrate including a first face, on which an active area is formed, and a second face opposite to the first face; an electronic element formed on the active area; a front wiring structure disposed on the first face of the substrate and connected to the electronic element; a trench capacitor filling at least a portion of a back trench extending into the substrate from the second face of the substrate; a back wiring structure disposed on the second face of the substrate and connected to the trench capacitor; and a through-via extending through the substrate to electrically connect the electronic element and the back wiring structure to each other.Type: ApplicationFiled: June 19, 2023Publication date: June 6, 2024Inventors: Hyung Jun JEON, Ho-Jin Lee
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Patent number: 11728200Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.Type: GrantFiled: December 4, 2019Date of Patent: August 15, 2023Assignee: Samsung Electronics Co., Ltd.Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
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Publication number: 20220367364Abstract: A semiconductor package includes a first semiconductor chip, which includes a first semiconductor substrate and a first bonding layer on the first semiconductor substrate. A second semiconductor chip includes a second semiconductor substrate, a second bonding layer bonded to the first bonding layer, and a chip-through-via which penetrates the second semiconductor substrate and is connected to the second bonding layer. A passivation film extends along an upper side of the second semiconductor chip and does not extend along side-faces of the second semiconductor chip. The chip-through-via penetrates the passivation film. A multiple-gap-fill film extends along the upper side of the first semiconductor chip, the side faces of the second semiconductor chip, and the side faces of the passivation film. The multiple-gap-fill films includes an inorganic filling film and an organic filling film which are sequentially stacked on the first semiconductor chip.Type: ApplicationFiled: February 25, 2022Publication date: November 17, 2022Inventors: HYUNG JUN JEON, KWANG JIN MOON, SON-KWAN HWANG
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Publication number: 20200373186Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.Type: ApplicationFiled: December 4, 2019Publication date: November 26, 2020Applicant: Samsung Electronics Co., Ltd.Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
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Patent number: 10580726Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.Type: GrantFiled: August 21, 2018Date of Patent: March 3, 2020Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Jin-Ho Chun, Seong-Min Son, Hyung-Jun Jeon, Kwang-Jin Moon, Jin-Ho An, Ho-Jin Lee, Atsushi Fujisaki
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Publication number: 20190131228Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.Type: ApplicationFiled: August 21, 2018Publication date: May 2, 2019Inventors: Jin-Ho CHUN, Seong-Min SON, Hyung-Jun JEON, Kwang-Jin MOON, Jin-Ho AN, Ho-Jin LEE, Atsushi FUJISAKI
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Patent number: 10153219Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.Type: GrantFiled: June 21, 2017Date of Patent: December 11, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-jun Jeon, Nae-in Lee, Byung-Iyul Park
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Publication number: 20180076103Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.Type: ApplicationFiled: June 21, 2017Publication date: March 15, 2018Inventors: Hyung-jun JEON, Nae-in LEE, Byung-lyul PARK
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Patent number: 9691685Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.Type: GrantFiled: May 25, 2016Date of Patent: June 27, 2017Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
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Publication number: 20170033032Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.Type: ApplicationFiled: May 25, 2016Publication date: February 2, 2017Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
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Patent number: 9107143Abstract: An apparatus and method connect an Access Point (AP) in a portable terminal. More particularly, an apparatus and method designate a group of searched peripheral APs, and attempt an access to an AP corresponding to a group selected by a user in a portable terminal. The apparatus includes a group set unit and an AP search unit. The group set unit sets items of peripheral APs to a group according to user's selection. After searching the peripheral APs at the time of AP connection, the AP search unit classifies an AP belonging to a selected item and connects to the classified AP.Type: GrantFiled: November 21, 2011Date of Patent: August 11, 2015Assignee: Samsung Electronics Co., LtdInventors: Jong-Seok Kim, Hyung-Jun Jeon
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Patent number: 8742930Abstract: Disclosed is a gate system arranged on two gate frames and detects a tag passing between the two gate frames, the gate system including at least two gate frames that are vertically arranged facing with each other; at least two antenna units that are arranged on the at least two gate frames, respectively; and a reader that is arranged on each of the at least two gate frames and enables the at least two antenna units to emit electromagnetic wave to an article passing between the at least two gate frames using a predetermined frequency signal, and obtains information stored in a tag using a signal that the at least two antenna units receives from the at least two antenna units.Type: GrantFiled: March 11, 2011Date of Patent: June 3, 2014Assignee: LS Industrial Systems Co., Ltd.Inventors: Jin Kuk Hong, Jeong Ki Ryoo, Jae Yul Choo, Hyung Jun Jeon
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Publication number: 20140145327Abstract: Semiconductor devices and methods for fabricating the same are provided. For example, the semiconductor device includes a substrate, a first contact pad formed on the substrate, an insulation layer formed on the substrate and including a first opening which exposes the first contact pad, a first bump formed on the first contact pad and electrically connected to the first contact pad, and a reinforcement member formed on the insulation layer and adjacent to a side surface of the first lower bump. The first bump includes a first lower bump and a first upper bump, which are sequentially stacked on the first contact pad.Type: ApplicationFiled: October 23, 2013Publication date: May 29, 2014Applicant: SAMSUNG ELECTRONICS CO., LTD.Inventors: Hyung-Jun JEON, Jae-Hyun PHEE, Byung-Lyul PARK, Ji-Soon PARK, Jeong-Gi JIN
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Patent number: 8633056Abstract: A method of manufacture of an integrated circuit package system includes forming a substrate with a device thereover, forming an encapsulation having a planar top surface to cover the device and the substrate spanning to an extraction side of the encapsulation, and forming a recess in the encapsulation from the planar top surface.Type: GrantFiled: March 12, 2010Date of Patent: January 21, 2014Assignee: Stats Chippac Ltd.Inventors: Hyung Jun Jeon, Tae Keun Lee, Sung Soo Kim
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Patent number: 8588337Abstract: Disclosed is a vector modulator. The vector modulator can control the amplitude and phase of an input signal, by not using amplitude variable attenuators but using phase shifters. Further, the vector modulator has a simple configuration and enables an input signal to be exactly modulated. Furthermore, the vector modulator can modulate the phase of an input signal throughout all areas in the polar coordinate system.Type: GrantFiled: January 31, 2011Date of Patent: November 19, 2013Assignee: LS Industrial Systems Co., Ltd.Inventors: Heon soo Choi, Chang su Choi, Hyung jun Jeon, Yeong chan Kim, Jae hwan Im, Jung ki Ruy
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Patent number: 8537881Abstract: Disclosed is an RF transceiver in which transmission and reception are simultaneously performed, wherein a magnitude of a transmission leakage signal mixed into a receiving signal is measured, the maximum and minimum scopes on I/Q vector phase-plane in which an offset vector exists is set using the measured magnitude of the transmission leakage signal, the offset vector offsetting the transmission leakage signal as much as possible, a detection area in which the offset vector exists is determined in the set scope, and the offset vector is detected.Type: GrantFiled: March 2, 2011Date of Patent: September 17, 2013Assignee: Nethom Co., Ltd.Inventors: Heon soo Choi, Chang su Choi, Hyung jun Jeon, Yeong chan Kim
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Patent number: 8451125Abstract: Disclosed is an RFID-based reader configured to allow a UHF band RFID reader unit to recognize an RFID tag in a short distance, and to minimize an erroneous recognition, the reader including a gate frame discretely installed at both sides of an entrance and exit, a parabolic surface type reflective plate perpendicularly installed inside of the gate frame, an array antenna arranged on the reflective plate for receiving a tag information transmitted from an RFID tag, and an RFID reader unit for controlling an operation of the array antenna and converting the tag information received from the array antenna to a tag data.Type: GrantFiled: October 19, 2010Date of Patent: May 28, 2013Assignee: LS Industrial Systems Co., Ltd.Inventors: Jin Kuk Hong, Jeong Ki Ryoo, Jae Yul Choo, Hyung Jun Jeon
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Patent number: 8400229Abstract: An vector modulator using a time delay and a phase shifter is disclosed, the vector modulator including a time delay (110) varying a phase of an input signal by time-delaying the input signal; a first coupler (120) converting the signal outputted in changed phase through the time delay to an I channel signal and a Q channel signal each having a 90° phase difference and outputting the I/Q channel signals; a first phase shifter (130) varying the phase of the I channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable I channel signal; a second phase shifter (140) varying the Q channel signal outputted from the first coupler within a predetermined phase range and outputting the phase-variable Q channel signal; and a second coupler (150) coupling phase-variable I/Q channel signals and outputting the coupled signals.Type: GrantFiled: March 7, 2011Date of Patent: March 19, 2013Assignee: LS Industrial Systems Co., Ltd.Inventors: Heon soo Choi, Chang su Choi, Hyung jun Jeon, Yeong chan Kim, Jae hwan Im, Jin Kuk Hong
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Patent number: 8368200Abstract: A method of manufacture of a shielded stacked integrated circuit packaging system includes: forming a first integrated circuit structure having a first substrate and a first integrated circuit die; mounting a shield over the first substrate and the first integrated circuit die; mounting a second integrated circuit structure having a second substrate and a second integrated circuit die over the shield; and forming a package encapsulation for covering the first integrated circuit die, the shield, and the second integrated circuit structure.Type: GrantFiled: August 17, 2011Date of Patent: February 5, 2013Assignee: STATS ChipPAC Ltd.Inventors: Ki Youn Jang, YoungMin Kim, Hyung Jun Jeon