Patents by Inventor Hyung Jun Jeon

Hyung Jun Jeon has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240379639
    Abstract: An example semiconductor package includes a structure, a first semiconductor chip disposed on an upper surface of the structure and electrically connected to the structure, a dummy semiconductor chip disposed on and contacting the upper surface of the structure, a molding layer surrounding a sidewall of the first semiconductor chip and a sidewall of the dummy semiconductor chip on the upper surface of the structure, a redistribution layer disposed on an upper surface of the first semiconductor chip, an upper surface of the dummy semiconductor chip, and an upper surface of the molding layer, a first through-via extending through the molding layer in a vertical direction and electrically connecting the structure and the redistribution layer, a second through-via extending through the dummy semiconductor chip in the vertical direction and electrically connecting the structure and the redistribution layer, and a capacitor disposed inside the dummy semiconductor chip.
    Type: Application
    Filed: December 27, 2023
    Publication date: November 14, 2024
    Inventors: Myung Joo Park, Hyung Jun Jeon, Pil-Kyu Kang
  • Patent number: 12125836
    Abstract: A display device includes a first conductive layer disposed on a substrate, a passivation layer disposed on the first conductive layer, a second conductive layer disposed on the passivation layer, a via layer disposed on the second conductive layer, a third conductive layer disposed on the via layer, the third conductive layer including a first electrode, a second electrode, a connection pattern, the first electrode, the second electrode, and the connection pattern being spaced apart from each other, and a light emitting element, a first end and a second end of the light emitting element being disposed on the first electrode and the second electrode, respectively, wherein the connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer and the passivation layer.
    Type: Grant
    Filed: December 26, 2023
    Date of Patent: October 22, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyung Jin Jeon, So Young Koo, Eok Su Kim, Hyung Jun Kim, Yun Yong Nam, Jun Hyung Lim
  • Patent number: 12107114
    Abstract: A display device includes first banks on a substrate and spaced apart from each other, a first electrode and a second electrode on the first banks and spaced apart from each other, a first insulating layer on the first electrode and the second electrode, and light emitting elements on the first insulating layer and each having ends on the first electrode and the second electrode. Each of the first banks includes a first pattern portion including concave portions and convex portions. The first pattern portions of the first banks are disposed on side surfaces of the first banks. The side surfaces are spaced apart and face each other. Each of the first electrode and the second electrode includes a second pattern portion on the first pattern portion and having a pattern shape corresponding to the first pattern portion on a surface thereof.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: October 1, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Hyung Jun Kim, So Young Koo, Eok Su Kim, Yun Yong Nam, Jun Hyung Lim, Kyung Jin Jeon
  • Publication number: 20240312718
    Abstract: A multilayer electronic component includes a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer; and an external electrode disposed on the body, wherein the external electrode includes an electrode layer connected to the internal electrode and including Cu, a first plating portion disposed on the electrode layer, and a second plating portion disposed on the first plating portion, and wherein the first plating portion includes a Ni layer in contact with the electrode layer, and an intermetallic compound layer disposed on the Ni layer and including an intermetallic compound including at least one of Ni and Sn.
    Type: Application
    Filed: February 21, 2024
    Publication date: September 19, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: So Jung AN, Hyung Jong CHOI, Jung Won PARK, Yoo Jeong LEE, Kwang Yeun WON, Woo Kyung SUNG, Byung Jun JEON, Chul Seung LEE
  • Publication number: 20240285557
    Abstract: The present invention relates to a therapeutic agent of a lipase inhibitor for a wide spectrum of RNA viral infections in humans and animals. More specifically, the lipase inhibitor can be used as a therapeutic agent for influenza A virus infection, bovine coronavirus infection, porcine epidemic diarrhea coronavirus infection, bovine rotavirus infection, porcine reproductive and respiratory syndrome virus infection, and sapoviral infection and furthermore, can be utilized as a therapeutic agent for various RNA viral infections in humans and animals, such as infections with SARS COV-1, MERS-COV, Zika virus, dengue fever virus, and hepatitis A and C viruses.
    Type: Application
    Filed: June 24, 2022
    Publication date: August 29, 2024
    Inventors: Kyoung Oh CHO, Tae ll JEON, Sun Woo LEE, Yeong Bin BAEK, Hyung Jun Kwon, Hueng Sik CHOI, Sang lk PARK, Muhammad SHARIF, Jeong Ah LIM
  • Publication number: 20240290540
    Abstract: Provided is a multilayer electronic component according to an example embodiment of the present disclosure including: a body including a dielectric layer and an internal electrode alternately disposed with the dielectric layer in a first direction, and including Ni; and an external electrode disposed on the body and connected to the internal electrode, wherein the external electrode includes a base electrode layer including Ni and Pd, and the internal electrode includes a first region, and a content of Pd included in the first region is greater than a content of Pd included in a remaining region, excluding the first region in the internal electrode.
    Type: Application
    Filed: February 9, 2024
    Publication date: August 29, 2024
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Hyung Duk Yun, Byung Jun Jeon, Chae Min Park, Yong Won Seo, Ho In Jun, A Ra Cho
  • Patent number: 12069918
    Abstract: A display device includes a substrate, a first conductive layer on the substrate and including a lower light blocking pattern and a first signal line, a buffer layer on the first conductive layer, a semiconductor layer on the buffer layer and including a first semiconductor pattern and a second semiconductor pattern separated from the first semiconductor pattern, an insulating layer on the semiconductor layer and including an insulating layer pattern, a second conductive layer on the insulating layer and including a second signal line, a planarization layer on the second conductive layer, and a third conductive layer on the planarization layer and including an anode electrode. The first semiconductor pattern is electrically connected to the lower light blocking pattern by the anode electrode, and at least a portion of the second semiconductor pattern is isolated from and overlaps each of the first signal line and the second signal line.
    Type: Grant
    Filed: August 4, 2023
    Date of Patent: August 20, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyung Jin Jeon, So Young Koo, Eok Su Kim, Hyung Jun Kim, Jun Hyung Lim
  • Patent number: 12068336
    Abstract: A display device and a method of manufacturing a display device are provided. The display device includes a first conductive layer on a substrate, a passivation layer disposed on the first conductive layer and exposing at least a part of the first conductive layer, a second conductive layer disposed on the passivation layer and covering an upper surface of the passivation layer, a via layer on the second conductive layer, a third conductive layer including a first electrode, a second electrode, and a connection pattern, and spaced apart from each other on the via layer, and a light emitting element having ends that are disposed on the first electrode and the second electrode, respectively. The connection pattern electrically connects the first conductive layer and the second conductive layer through a first contact hole penetrating the via layer.
    Type: Grant
    Filed: September 8, 2021
    Date of Patent: August 20, 2024
    Assignee: SAMSUNG DISPLAY CO., LTD.
    Inventors: Kyung Jin Jeon, So Young Koo, Eok Su Kim, Hyung Jun Kim, Yun Yong Nam, Jun Hyung Lim
  • Publication number: 20240186247
    Abstract: A semiconductor device includes: a substrate including a first face, on which an active area is formed, and a second face opposite to the first face; an electronic element formed on the active area; a front wiring structure disposed on the first face of the substrate and connected to the electronic element; a trench capacitor filling at least a portion of a back trench extending into the substrate from the second face of the substrate; a back wiring structure disposed on the second face of the substrate and connected to the trench capacitor; and a through-via extending through the substrate to electrically connect the electronic element and the back wiring structure to each other.
    Type: Application
    Filed: June 19, 2023
    Publication date: June 6, 2024
    Inventors: Hyung Jun JEON, Ho-Jin Lee
  • Patent number: 11728200
    Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.
    Type: Grant
    Filed: December 4, 2019
    Date of Patent: August 15, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
  • Publication number: 20220367364
    Abstract: A semiconductor package includes a first semiconductor chip, which includes a first semiconductor substrate and a first bonding layer on the first semiconductor substrate. A second semiconductor chip includes a second semiconductor substrate, a second bonding layer bonded to the first bonding layer, and a chip-through-via which penetrates the second semiconductor substrate and is connected to the second bonding layer. A passivation film extends along an upper side of the second semiconductor chip and does not extend along side-faces of the second semiconductor chip. The chip-through-via penetrates the passivation film. A multiple-gap-fill film extends along the upper side of the first semiconductor chip, the side faces of the second semiconductor chip, and the side faces of the passivation film. The multiple-gap-fill films includes an inorganic filling film and an organic filling film which are sequentially stacked on the first semiconductor chip.
    Type: Application
    Filed: February 25, 2022
    Publication date: November 17, 2022
    Inventors: HYUNG JUN JEON, KWANG JIN MOON, SON-KWAN HWANG
  • Publication number: 20200373186
    Abstract: A wafer bonding apparatus is provided includes a lower support plate configured to structurally support a first wafer on an upper surface of the lower support plate; a lower structure adjacent to the lower support plate and movable in a vertical direction that is perpendicular to the upper surface of the lower support plate, an upper support plate configured to structurally support a second wafer on a lower surface of the lower support plate, and an upper structure adjacent to the upper support plate and movable in the vertical direction.
    Type: Application
    Filed: December 4, 2019
    Publication date: November 26, 2020
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Hoe Chul Kim, Seok Ho Kim, Tae Yeong Kim, Hoon Joo Na, Hyung Jun Jeon
  • Patent number: 10580726
    Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: March 3, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jin-Ho Chun, Seong-Min Son, Hyung-Jun Jeon, Kwang-Jin Moon, Jin-Ho An, Ho-Jin Lee, Atsushi Fujisaki
  • Publication number: 20190131228
    Abstract: A semiconductor device and a method of manufacturing the same, the device including a through-hole electrode structure extending through a substrate; a redistribution layer on the through-hole electrode structure; and a conductive pad, the conductive pad including a penetrating portion extending through the redistribution layer; and a protrusion portion on the penetrating portion, the protrusion portion protruding from an upper surface of the redistribution layer, wherein a central region of an upper surface of the protrusion portion is flat and not closer to the substrate than an edge region of the upper surface of the protrusion portion.
    Type: Application
    Filed: August 21, 2018
    Publication date: May 2, 2019
    Inventors: Jin-Ho CHUN, Seong-Min SON, Hyung-Jun JEON, Kwang-Jin MOON, Jin-Ho AN, Ho-Jin LEE, Atsushi FUJISAKI
  • Patent number: 10153219
    Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.
    Type: Grant
    Filed: June 21, 2017
    Date of Patent: December 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Hyung-jun Jeon, Nae-in Lee, Byung-Iyul Park
  • Publication number: 20180076103
    Abstract: A semiconductor package of a package on package type includes a lower package including a printed circuit board (PCB) substrate including a plurality of base layers and a cavity penetrating the plurality of base layers, a first semiconductor chip in the cavity. a redistribution structure on a first surface of the PCB substrate and on an active surface of the first semiconductor chip, a first cover layer covering the redistribution structure, and the second cover layer covering a second surface of the PCB substrate and an inactive surface of the first semiconductor chip, and an upper package on the second cover layer of the lower package and including a second semiconductor chip.
    Type: Application
    Filed: June 21, 2017
    Publication date: March 15, 2018
    Inventors: Hyung-jun JEON, Nae-in LEE, Byung-lyul PARK
  • Patent number: 9691685
    Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.
    Type: Grant
    Filed: May 25, 2016
    Date of Patent: June 27, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
  • Publication number: 20170033032
    Abstract: A semiconductor device includes a substrate having a die region and a scribe region surrounding the die region, a plurality of via structures penetrating through the substrate in the die region, a portion of the via structure being exposed over a surface of the substrate, and a protection layer pattern structure provided on the surface of the substrate surrounding a sidewall of the exposed portion of the via structure and having a protruding portion covering at least a portion of the scribe region adjacent to the via structure.
    Type: Application
    Filed: May 25, 2016
    Publication date: February 2, 2017
    Inventors: Kyu-Ha Lee, Hyung-Jun Jeon, Jum-Yong Park, Byung-Lyul Park, Ji-Soon Park, Jin-Ho An, Jin-Ho Chun
  • Patent number: 9107143
    Abstract: An apparatus and method connect an Access Point (AP) in a portable terminal. More particularly, an apparatus and method designate a group of searched peripheral APs, and attempt an access to an AP corresponding to a group selected by a user in a portable terminal. The apparatus includes a group set unit and an AP search unit. The group set unit sets items of peripheral APs to a group according to user's selection. After searching the peripheral APs at the time of AP connection, the AP search unit classifies an AP belonging to a selected item and connects to the classified AP.
    Type: Grant
    Filed: November 21, 2011
    Date of Patent: August 11, 2015
    Assignee: Samsung Electronics Co., Ltd
    Inventors: Jong-Seok Kim, Hyung-Jun Jeon
  • Patent number: 8742930
    Abstract: Disclosed is a gate system arranged on two gate frames and detects a tag passing between the two gate frames, the gate system including at least two gate frames that are vertically arranged facing with each other; at least two antenna units that are arranged on the at least two gate frames, respectively; and a reader that is arranged on each of the at least two gate frames and enables the at least two antenna units to emit electromagnetic wave to an article passing between the at least two gate frames using a predetermined frequency signal, and obtains information stored in a tag using a signal that the at least two antenna units receives from the at least two antenna units.
    Type: Grant
    Filed: March 11, 2011
    Date of Patent: June 3, 2014
    Assignee: LS Industrial Systems Co., Ltd.
    Inventors: Jin Kuk Hong, Jeong Ki Ryoo, Jae Yul Choo, Hyung Jun Jeon