Abstract: Disclosed herein are engineered rhizobia having nif clusters that enable the fixation of nitrogen under free-living conditions, as well as ammonium and oxygen tolerant nitrogen fixation under free-living conditions. Also provided are methods for producing nitrogen for consumption by a cereal crop using these engineered rhizobia.

Abstract: A power semiconductor device includes a semiconductor structure comprising an active region, a plurality of gates that extend in a first direction in or on the active region of the semiconductor structure, at least one integrated polysilicon device in or on the semiconductor structure adjacent the active region, and a gate connector electrically connecting the plurality of gates. The gate connector is in or on the semiconductor structure between the at least one integrated polysilicon device and the plurality of gates. The at least one integrated polysilicon device is electrically isolated from the gate connector devoid of an inter-polysilicon dielectric layer therebetween. Related devices and fabrication methods are also discussed.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device comprises a semiconductor layer structure that has a gate trench therein and a source metallization layer on the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a trench shield that has a second conductivity type, the trench shield positioned underneath the gate trench, and a trench shield connection pattern that has the second conductivity type, the trench shield connection pattern electrically connecting the trench shield to the source metallization layer, where the trench shield connection pattern extends deeper into the semiconductor layer structure than the trench shield.

Abstract: A semiconductor device includes a device active region comprising a first well, at least a portion of the first well being part of a first metal-oxide-semiconductor field-effect transistor (MOSFET), and a sensor region comprising a second well, at least a portion of the second well being part of a second MOSFET configured to mirror a current in the first MOSFET. A distance between an outer edge of the second well and an inner edge of the first well is constant or the distance decreases approaching one or more vertices of the second well.

Abstract: A semiconductor device comprises a semiconductor layer structure comprising a drift region having a first conductivity type, a well region having a second conductivity type on the drift region, and a first JFET region having the first conductivity type, and a gate trench extending into the semiconductor layer structure. An upper surface of the first JFET region is positioned below the gate trench. A first conductivity dopant concentration of the first JFET region exceeds a first conductivity dopant concentration of the drift region.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a junction field-effect transistor (JFET) region of a first conductivity type, a well region of a second conductivity type on the JFET region, a source region of the first conductivity type on the well region and a plurality of support shields of the second conductivity type. The support shields are spaced apart from one another in a first direction parallel to an upper surface of the semiconductor layer structure and extend through the source region, the well region and the JFET region. The semiconductor device further includes a trenched gate structure formed in the semiconductor layer structure between a pair of adjacent support shields. Edges of at least two of the JFET region, the well region and the source region are aligned in a second direction perpendicular to the first direction.

Abstract: A power semiconductor device includes a semiconductor structure having a drift region of a first conductivity type. Gate trenches respectively comprising sidewalls and a bottom surface therebetween extend in a first direction in the semiconductor structure, and support shielding structures of a second conductivity type extend in the first direction in the semiconductor structure spaced apart from the sidewalls of the gate trenches. At least two of the support shielding structures are between immediately adjacent pairs of the gate trenches, or at least two of the gate trenches are between immediately adjacent pairs of the support shielding structures. For example, the support shielding structures may include first and second support shielding structures that are free of the gate trenches therebetween, or the gate trenches may include first and second gate trenches that are free of the support shielding structures therebetween. Related devices and fabrication methods are also discussed.

Abstract: Semiconductor devices are provided that comprise a semiconductor layer structure that comprises a drift region having a first conductivity type, a channel region having a second conductivity type, and a source region having the first conductivity type. A gate trench extends into an upper surface of the semiconductor layer structure. The channel region horizontally overlaps both the gate trench and the source region.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure that comprises a drift region having a first conductivity type and an implanted region having a second conductivity type on the drift region. First and second gate trench sections extend into the semiconductor layer structure. A first maximum depth into the semiconductor layer structure of a first portion of the implanted region that is between the first gate trench section and the second gate trench section is different than a second maximum depth into the semiconductor layer structure of a second portion of the implanted region that extends downwardly underneath the first gate trench section.

Abstract: A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.

Abstract: Disclosed herein are engineered rhizobia having nif clusters that enable the fixation of nitrogen under free-living conditions, as well as ammonium and oxygen tolerant nitrogen fixation under free-living conditions. Also provided are methods for producing nitrogen for consumption by a cereal crop using these engineered rhizobia.

Abstract: A secure booting apparatus according to an embodiment for solving the problems to be solved by the present invention includes: a memory configured to store encrypted data, an encrypted header, and a symmetric key; and a processor configured to generate decrypted data and a decrypted header by applying a symmetric key algorithm using the symmetric key to the encrypted data and encrypted header, to include a public key and a pre key generated from the public key in the decrypted header, to generate a comparison hashed message by applying a hash algorithm to the decrypted data, to generate a final verification value by applying a public key algorithm using the public key and the pre key to the decrypted header, to compare the comparison hashed message with the final verification value, and to determine that booting has failed if the comparison hashed message and the final verification value are different from each other.

Abstract: Semiconductor devices and methods of forming the devices are provided. Semiconductor devices include a semiconductor layer structure comprising a trench in an upper surface thereof, a dielectric layer in a lower portion of the trench, and a gate electrode in the trench and on the dielectric layer opposite the semiconductor layer structure. The trench may include rounded upper corner and a rounded lower corner. A center portion of a top surface of the dielectric layer may be curved, and the dielectric layer may be on opposed sidewalls of the trench. The dielectric layer may include a bottom dielectric layer on a bottom surface of the trench and on lower portions of the sidewalls of the trench and a gate dielectric layer on upper portions of the sidewalls of the trench and on the bottom dielectric layer.

Abstract: Semiconductor devices and methods of forming a semiconductor device that includes a polysilicon layer that may improve device reliability and/or a functioning of the device. An example device may include a wide band-gap semiconductor layer structure including a drift region that has a first conductivity type; a plurality of gate trenches in an upper portion of the semiconductor layer structure, each gate trench having a bottom surface, a first sidewall, a second sidewall, and an upper opening; and a plurality of polysilicon layers, each polysilicon layer on the second sidewall of a respective gate trench.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure that includes a drift layer having a first conductivity type, a gate trench that extends to a first depth into an upper surface of the semiconductor layer structure, a gate electrode in the gate trench, a support shield trench that extends to a second depth into the upper surface of the semiconductor layer structure, where the second depth is less than the first depth, and a source metallization layer on the upper surface of the semiconductor layer structure and extending into the support shield trench.

Abstract: A semiconductor device comprises a silicon carbide based semiconductor layer structure and a first gate trench extending into an upper portion of the semiconductor layer structure. The semiconductor layer structure comprises a drift region having a first conductivity type, a well layer having a second conductivity type, and a support shield having the second conductivity type. A width of a first segment of the support shield that is deeper in the semiconductor layer structure than the well layer and less deep in the semiconductor layer structure than a bottom of the first gate trench decreases with increasing distance from the well region.

Abstract: Semiconductor devices are provided. In one example, a semiconductor device includes a semiconductor structure. The semiconductor device includes a gate finger in a gate trench in the semiconductor structure. The gate trench extends a length in the semiconductor structure. The gate trench has a first portion having a first width and a second portion having a second width. The second width is different than the first width.

Abstract: A apparatus for manufacturing a display device includes: a stage for supporting a display module including a display panel, a cover window, and a flexible printed circuit board; and an adsorption unit disposed at one side of the stage, the adsorption unit configured to be moved in a horizontal direction such that a distance between the stage and the adsorption unit is adjusted, wherein the adsorption unit is configured to adsorb and support the flexible printed circuit board connected to the display panel.

Abstract: Power semiconductor devices are provided. In one example, the power semiconductor device includes a semiconductor structure includes an active region and an inactive region, the active region includes a plurality of unit cells. The power semiconductor device includes a gate structure, wherein at least a portion of the gate structure is on the inactive region. The power semiconductor device includes a first shunt contact structure at least partially on the inactive region. The power semiconductor device includes a second shunt contact structure at least partially on the inactive region. The power semiconductor device includes a balancing shunt structure at least partially on the inactive region.