Abstract: Image sensors and fabrication methods thereof are provided. An image sensor includes a semiconductor substrate including pixel regions, and a fence structure that defines openings that correspond to the pixel regions. A fence structure includes a metal pattern on the semiconductor substrate, a low-refractive pattern on the metal pattern, and a metal oxide pattern between the metal pattern and the low-refractive pattern.

Abstract: A semiconductor device includes a semiconductor layer structure having a drift region of a first conductivity type and a well region of a second conductivity type above the drift region. A gate is provided on the semiconductor layer structure adjacent the well region. A buried shielding structure of the second conductivity type is provided under the well region and separated from the well region by a portion of the drift region. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device and an image sensor are disclosed. The semiconductor device includes: a gate pattern disposed on a substrate; a first interlayer insulating layer on a sidewall of the gate pattern; a second interlayer insulating layer on the gate pattern and the first interlayer insulating layer; and a first contact plug passing through the second interlayer insulating layer and the first interlayer insulating layer and being in contact with the substrate, where the first contact plug comprises a first contact part in the first interlayer insulating layer and a second contact part in the second interlayer insulating layer, a density of the first interlayer insulating layer is smaller than a density of the second interlayer insulating layer, the first contact part of the first contact plug has a first width, and the second contact part of the first contact plug has a second width smaller than the first width.

Abstract: A power semiconductor device includes semiconductor layer structure comprising a semiconductor drift region of a first conductivity type and an edge termination region comprising a plurality of guard rings of a second conductivity type. The guard rings extend into a surface of the semiconductor drift region. The guard rings respectively comprise a first portion adjacent the surface and a second portion spaced from the surface, where the first portion is wider than the second portion. Related devices and fabrication methods are also discussed.

Abstract: An apparatus for attaching a display panel includes a panel mount which receives a panel bottom cover facing corner portions of the display panel which are extended bent from a front surface of the display panel, and a pressing module which provides a pressing force to the panel bottom cover which is received in the panel mount and faces the corner portions of the display panel. The pressing module includes a pressing pad which applies the pressing force to the panel bottom cover at the corner portions of the display panel to attach the panel bottom cover to the display panel at the corner portions thereof.

Abstract: A vertical semiconductor device includes a substrate, a drift region over the substrate, an upper region on the drift region, a top surface over the upper region and being substantially planar, and a series of implants of a second dopant in the upper region, such that each implant of the series of implants is located at a different depth below the top surface. The series of implants forms at least two gate region. The substrate and the drift region are doped with a first dopant of a first polarity. The second dopant has a second polarity opposite that of the first polarity. At least a portion of a channel region is provided between the at least two gate regions, and a conducting gap is defined within the channel region and between opposing sidewalls of the at least two gate regions.

Abstract: A semiconductor device includes a vertical transistor and a body diode. Various improvements to the semiconductor device allow for improved performance of the body diode, in particular to reduced snappiness and increased softness.

Abstract: A display device includes a display panel comprises a display area and a non-display area surrounding the display area; a cover panel disposed on a rear surface of the display panel and comprising a front surface, a first side surface connected to the front surface and bent along a first bending line, a second side surface connected to the front surface and bent along a second bending line intersecting the first bending line, and a first corner located between the first side surface and the second side surface; and an alignment notch defined at the first corner of the cover panel.

Abstract: A secure booting apparatus according to an embodiment for solving the problems to be solved by the present invention includes: a memory configured to store encrypted data, an encrypted header, and a symmetric key; and a processor configured to generate decrypted data and a decrypted header by applying a symmetric key algorithm using the symmetric key to the encrypted data and encrypted header, to include a public key and a pre key generated from the public key in the decrypted header, to generate a comparison hashed message by applying a hash algorithm to the decrypted data, to generate a final verification value by applying a public key algorithm using the public key and the pre key to the decrypted header, to compare the comparison hashed message with the final verification value, and to determine that booting has failed if the comparison hashed message and the final verification value are different from each other.

Abstract: A precursor for a vertical semiconductor device is provided with a substrate, a drift region over the substrate, and an upper precursor region over the drift region. The top surface of the precursor is substantially planar, and the substrate and the drift region are doped with a first dopant of a first polarity. In a first embodiment, a series of implants with a second dopant is provided in the upper precursor region via the top surface to form each of at least two gate regions such that each implant of the series of implants is provided at a different depth below the top surface. In a second embodiment, a series of implants with the first dopant is provided in the upper precursor region via the top surface to form a channel region that has at least a portion between two gate regions.

Abstract: A semiconductor device includes a semiconductor layer structure comprising a gate trench formed in an upper surface thereof, a gate finger in the gate trench, a supplemental dielectric layer on an upper surface of the gate finger and vertically overlaps the gate trench, and a gate connector on an upper surface of the supplemental dielectric layer and on an upper surface of the gate finger.

Abstract: A method of forming ohmic contacts on a semiconductor structure having a p-type region and an n-type region includes depositing a first metal on the n-type region, annealing the structure at a first contact anneal temperature to form a first ohmic contact on the n-type region, depositing a second metal on the first ohmic contact and on the p-type region, and annealing the structure at a second contact anneal temperature, less than the first contact anneal temperature, to form a second ohmic contact on the p-type region.

Abstract: A wide band-gap semiconductor layer structure is provided that comprises a drift region having a first conductivity type and a plurality of source regions having the first conductivity type on the drift region. A plurality of trenches are provided in an upper surface of the wide band-gap semiconductor layer structure. Second conductivity type dopants are implanted into the wide band-gap semiconductor layer structure to simultaneously form well regions underneath the source regions and trench shielding regions underneath the trenches, the well regions and the trench shielding regions each having a second conductivity type.

Abstract: A power semiconductor device has a semiconductor layer structure that includes a silicon carbide drift region having a first conductivity type, first and second wells in the silicon carbide drift region that are doped with dopants having a second conductivity type, and a JFET region between the first and second wells. The first and second wells each include a main well and a side well that is between the main well and the JFET region, and each side well includes a respective channel region. A doping concentration of the JFET region exceeds a doping concentration of the silicon carbide drift region, and a minimum width of an upper portion of the JFET region is greater than a minimum width of a lower portion of the JFET region.

Abstract: A power semiconductor device comprises a semiconductor layer structure having a wide band-gap drift region having a first conductivity type, a gate trench having first and second opposed sidewalls that extend in a first direction in an upper portion of the semiconductor layer structure, first and second well regions having a second conductivity type in the upper portion of the semiconductor layer structure, the first well region comprising part of the first sidewall and the second well region comprising part of the second sidewall. A deep shielding region having the second conductivity type is provided underneath the gate trench, and a plurality of deep shielding connection patterns that have the second conductivity type are provided that electrically connect the deep shielding region to the first and second well regions. The deep shielding connection patterns are spaced apart from each other along the first direction.

Abstract: A vertical semiconductor and method for fabricating the same is disclosed. In one embodiment, fabrication entails providing a precursor comprising a substrate and a drift region over the substrate. A plurality of trenches is etched into the drift region from a top surface of the drift region such that a plurality of mesas remains in an upper portion of the drift region. The plurality of trenches is then filled with a first material. A vertical semiconductor device includes a plurality of mesas extends from an upper portion of the drift region, wherein there are no regrowth interfaces between the drift region and the plurality of mesas. A first material fills the trenches between each one of the plurality of mesas. At least one first contact over at least one of the plurality of mesas. At least one second contact over a bottom surface of the substrate.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type and a well region of a second conductivity type, a plurality of gate trenches including respective gate insulating layers and gate electrodes therein extending into the drift region, respective shielding patterns of the second conductivity type in respective portions of the drift region adjacent the gate trenches, and respective conduction enhancing regions of the first conductivity type in the respective portions of the drift region. The drift region comprises a first concentration of dopants of the first conductivity type, and the respective conduction enhancing regions comprise a second concentration of the dopants of the first conductivity type that is higher than the first concentration. Related devices and fabrication methods are also discussed.

Abstract: A semiconductor device includes a device region and an on-chip sensor region, such as an on-chip current sensor region. The semiconductor device further includes a transition region formed between the device region and the sensor region. A gate contact extends across the transition region. A conductive segment may be formed on the gate contact in the transition region to reduce a resistivity of the material used to form the gate contact. Additionally or alternatively, an isolation region may be formed under the gate contact between a first isolated well region in the device region and a second isolated well region in the sensor region. The isolation region isolates the first isolated well region from the second isolated well region to prevent current in the device region from propagating into the sensor region.

Abstract: A power semiconductor device includes a semiconductor layer structure comprising a drift region of a first conductivity type, and a gate trench extending into the drift region. The gate trench includes sidewalls and a bottom surface therebetween. A bottom shielding structure of a second conductivity type is provided under the bottom surface of the gate trench. First and second support shielding structures of the second conductivity type extend into the drift region on opposing sides of the gate trench and are spaced apart from the sidewalls thereof. A material composition, distance of extension into the drift region relative to a surface of the semiconductor layer structure, and/or dopant concentration of the bottom shielding structure may be different from that of the first and second support shielding structures. Related devices and fabrication methods are also discussed.

Abstract: A power semiconductor device comprises a semiconductor layer structure comprising a drift region that comprises a wide band-gap semiconductor material and has a first conductivity type, a first gate structure and an adjacent second gate structure in an upper portion of the semiconductor layer structure, a deep shielding region in the drift region, and a connection region protruding upwardly from the deep shielding region and separating the first gate structure and the second gate structure from each other. The deep shielding region extends from underneath the first gate structure to underneath the second gate structure, and the deep shielding region has a second conductivity type that is different from the first conductivity type.