Patents by Inventor Hyung-sang Park
Hyung-sang Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240123370Abstract: An ion filter for circulating coolant in a fuel cell stack of a fuel cell vehicle includes a housing including an inlet configured so that a fluid is introduced and an outlet configured so that the fluid is discharged, a filter element accommodated in the housing to filter the fluid, a valve assembly provided on the inlet and configured to operate the flow of the fluid introduced into the housing through the inlet to be allowed or blocked, and a gate member provided in the housing and configured to adjust an operation of the valve assembly.Type: ApplicationFiled: March 2, 2023Publication date: April 18, 2024Inventors: Kyeong Jun BAEK, Sun Ae Park, Hun Woo Park, Hyung Geun Cho, Young Sang Cho, Sang Pil Byun
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Publication number: 20240018649Abstract: An embodiment powder-surface treatment apparatus includes a housing defining an internal space, a main chamber installed in the internal space and defining an accommodation space in which a surface treatment process is performable using ALD, an injection unit provided on a first end portion of the main chamber, a plurality of sub-chambers arranged in a stack on top of each other in a multi-step configuration along the accommodation space in the main chamber in a state where an internal space in each of the plurality of sub-chambers is filled with a powder, a discharging unit provided on a second end portion of the main chamber, a loading apparatus configured to load a new sub-chamber into the accommodation space in the main chamber, and an unloading apparatus configured to unload and discharge at least one of the plurality of sub-chambers from the accommodation space to the outside.Type: ApplicationFiled: December 29, 2022Publication date: January 18, 2024Inventors: Seung Jeong Oh, Woong Pyo Hong, Jung Yeon Park, Chae Woong Kim, Hyung Sang Park
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Publication number: 20230132914Abstract: Provided are powder atomic layer deposition (ALD) equipment capable of increasing deposition uniformity of powder by using a gas supply sequence with or without an impeller or a vibration generator, and a gas supply method thereof, the powder ALD equipment including a process chamber having an accommodation space therein to accommodate powder, a gas supplier for sequentially supplying a plurality of gases to the powder, and a gas exhauster for exhausting, to outside, the gases discharged from the process chamber, wherein the gas supplier includes a gas supply plate, a first gas supply line, a first valve, edge valves, and a gas supply sequence controller.Type: ApplicationFiled: May 13, 2021Publication date: May 4, 2023Inventors: Chae Woong KIM, Su Han SONG, Hyung Sang PARK
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Patent number: 11534772Abstract: The present disclosure relates to a trap device for a powder coating apparatus. The trap device includes a body part including an inlet through which exhaust gas containing lost powder is introduced, an outlet through which the exhaust gas is discharged, and an interior space in communication with the inlet and the outlet and a trap part that is located in the interior space of the body part and that traps the lost powder contained in the exhaust gas by a magnetic force.Type: GrantFiled: April 16, 2020Date of Patent: December 27, 2022Assignees: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, ISAC RESEARCH INC.Inventors: Woong Pyo Hong, Jung Yeon Park, Chae Woong Kim, Hyun Seok Cha, Hyung Sang Park
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Publication number: 20220145452Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.Type: ApplicationFiled: January 25, 2022Publication date: May 12, 2022Inventors: Tae Ho Yoon, Hyung Sang Park, Yong Min Yoo
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Patent number: 11261523Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.Type: GrantFiled: March 18, 2020Date of Patent: March 1, 2022Assignee: ASM KOREA LTD.Inventors: Tae Ho Yoon, Hyung Sang Park, Yong Min Yoo
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Publication number: 20210162428Abstract: The present disclosure relates to a trap device for a powder coating apparatus. The trap device includes a body part including an inlet through which exhaust gas containing lost powder is introduced, an outlet through which the exhaust gas is discharged, and an interior space in communication with the inlet and the outlet and a trap part that is located in the interior space of the body part and that traps the lost powder contained in the exhaust gas by a magnetic force.Type: ApplicationFiled: April 16, 2020Publication date: June 3, 2021Inventors: Woong Pyo Hong, Jung Yeon Park, Chae Woong Kim, Hyun Seok Cha, Hyung Sang Park
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Publication number: 20200385859Abstract: Methods of depositing a silicon oxide film are disclosed. One embodiment is a plasma enhanced atomic layer deposition (PEALD) process that includes supplying a vapor phase silicon precursor, such as a diaminosilane compound, to a substrate, and supplying oxygen plasma to the substrate. Another embodiment is a pulsed hybrid method between atomic layer deposition (ALD) and chemical vapor deposition (CVD). In the other embodiment, a vapor phase silicon precursor, such as a diaminosilane compound, is supplied to a substrate while ozone gas is continuously or discontinuously supplied to the substrate.Type: ApplicationFiled: March 18, 2020Publication date: December 10, 2020Inventors: Tae Ho Yoon, Hyung Sang Park, Yong Min Yoo
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Publication number: 20200263299Abstract: A surface treatment apparatus includes a chamber defining an accommodation space therein, an injection part provided at a first end of the chamber so as to inject gas into the accommodation space, a discharge part provided at a second end of the chamber that is opposite the first end so as to discharge unreacted gas from the accommodation space, and at least one subchamber loaded in the accommodation space in the chamber between the first end and the second end, where powder is charged in the subchamber, and the subchamber includes a mesh structure provided in at least one surface of the subchamber so as to allow the gas to be introduced into the subchamber, and the subchamber is movable from the first end to the second end.Type: ApplicationFiled: June 4, 2019Publication date: August 20, 2020Inventors: Woong Pyo Hong, Seung Jeong Oh, Jung Yeon Park, Jin Hyeok Cha, Hyung Sang Park, Chae Woong Kim, Tae Ho Yoon, Kun Woo Park
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Publication number: 20180274096Abstract: Disclosed is an atomic layer deposition system and method, the system including a chamber having a first accommodation space to accommodate a first target substrate, and a first gas supplier mounted in the chamber to supply a first gas to the first target substrate, wherein the first gas supplier includes a first fixed block having a rotation space therein and including a (1-1)st passage provided in a first direction of the rotation space and a (1-2)nd passage provided in a second direction of the rotation space, and a first rotatable pipe having a first gas channel therein, having a pipe shape including at least one first gas outlet at a side thereof, and rotatably mounted in the rotation space of the first fixed block to connect the first gas outlet to the (1-1)st or (1-2)nd passage of the first fixed block.Type: ApplicationFiled: March 23, 2018Publication date: September 27, 2018Inventors: Hyung Sang PARK, Tae Ho YOON, Ji Hye KIM
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Patent number: 8912101Abstract: A method for forming a silicon-containing dielectric film on a substrate by atomic layer deposition (ALD) includes: providing two precursors, one precursor containing a halogen in its molecule, another precursor containing a silicon but no halogen in its molecule, adsorbing a first precursor, which is one of the two precursors onto a substrate to deposit a monolayer of the first precursor; adsorbing a second precursor, which is the other of the two precursors onto the monolayer of the first precursor to deposit a monolayer of the second precursor; and exposing the monolayer of the second precursor to radicals of a reactant to cause surface reaction with the radicals to form a compound monolayer of a silicon-containing film.Type: GrantFiled: March 13, 2013Date of Patent: December 16, 2014Assignee: ASM IP Holding B.V.Inventors: Naoto Tsuji, Atsuki Fukazawa, Noboru Takamure, Suvi Haukka, Antti Juhani Niskanen, Hyung Sang Park
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Patent number: 8896133Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.Type: GrantFiled: April 25, 2013Date of Patent: November 25, 2014Assignee: STATS ChipPAC, Ltd.Inventors: SungWon Cho, KiYoun Jang, YongHee Kang, Hyung Sang Park
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Patent number: 8778083Abstract: A deposition apparatus according to an exemplary embodiment of the present invention is a lateral-flow deposition apparatus in which in which a process gas flows between a surface where a substrate is disposed and the opposite surface, substantially in parallel with the substrate. The lateral-flow deposition apparatus includes: a substrate support that moves up/down and rotates the substrate while supporting the substrate; a reactor cover that defines a reaction chamber by contacting the substrate support; and a substrate support lifter and a substrate support rotator that move the substrate support.Type: GrantFiled: July 21, 2010Date of Patent: July 15, 2014Assignee: ASM Genitech Korea Ltd.Inventors: Ki Jong Kim, Yong Min Yoo, Jung Soo Kim, Hyung Sang Park, Seung Woo Choi, Jeong Ho Lee, Dong Rak Jung
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Patent number: 8747948Abstract: A deposition apparatus configured to form a thin film on a substrate includes: a reactor wall; a substrate support positioned under the reactor wall; and a showerhead plate positioned above the substrate support. The showerhead plate defines a reaction space together with the substrate support. The apparatus also includes one or more gas conduits configured to open to a periphery of the reaction space at least while an inert gas is supplied therethrough. The one or more gas conduits are configured to supply the inert gas inwardly toward the periphery of the substrate support around the reaction space. This configuration prevents reactant gases from flowing between a substrate and the substrate support during a deposition process, thereby preventing deposition of an undesired thin film and impurity particles on the back side of the substrate.Type: GrantFiled: January 9, 2012Date of Patent: June 10, 2014Assignee: ASM Genitech Korea Ltd.Inventors: Hyung Sang Park, Seung Woo Choi, Jong Su Kim, Dong Rak Jung, Jeong Ho Lee, Chun Soo Lee
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Publication number: 20130244446Abstract: A method for forming a silicon-containing dielectric film on a substrate by atomic layer deposition (ALD) includes: providing two precursors, one precursor containing a halogen in its molecule, another precursor containing a silicon but no halogen in its molecule, adsorbing a first precursor, which is one of the two precursors onto a substrate to deposit a monolayer of the first precursor; adsorbing a second precursor, which is the other of the two precursors onto the monolayer of the first precursor to deposit a monolayer of the second precursor; and exposing the monolayer of the second precursor to radicals of a reactant to cause surface reaction with the radicals to form a compound monolayer of a silicon-containing film.Type: ApplicationFiled: March 13, 2013Publication date: September 19, 2013Applicant: ASM IP HOLDING B.V.Inventors: Naoto Tsuji, Atsuki Fukazawa, Noboru Takamure, Suvi Haukka, Antti Juhani Niskanen, Hyung Sang Park
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Publication number: 20130234324Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.Type: ApplicationFiled: April 25, 2013Publication date: September 12, 2013Applicant: STATS ChipPAC, Ltd.Inventors: SungWon Cho, KiYoun Jang, YongHee Kang, Hyung Sang Park
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Patent number: 8502391Abstract: A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer.Type: GrantFiled: December 8, 2011Date of Patent: August 6, 2013Assignee: STATS ChipPAC, Ltd.Inventors: Hyung Sang Park, Sung Soo Kim, SungWon Cho
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Patent number: 8492197Abstract: A semiconductor device has a first substrate and first conductive pillars formed over the first substrate. Second conductive pillars are formed over the first substrate alternating with the first conductive pillars. The second conductive pillars are vertically offset with respect to the first conductive pillars. First BOT interconnect sites are formed over a second substrate. Second BOT interconnect sites are formed over the second substrate alternating with the first interconnect sites. The second interconnect sites are vertically offset with respect to the first interconnect sites. The first substrate is mounted to the second substrate such that the first conductive pillars are aligned with and electrically connected to the first interconnect sites and the second conductive pillars are aligned with and electrically connected to the second interconnect sites. An underfill material is deposited between the first and second substrates. The first substrate can be a flipchip type semiconductor device.Type: GrantFiled: August 17, 2010Date of Patent: July 23, 2013Assignee: STATS ChipPAC, Ltd.Inventors: SungWon Cho, KiYoun Jang, YongHee Kang, Hyung Sang Park
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Publication number: 20130147053Abstract: A semiconductor device includes a first carrier having a first resin disposed over the first carrier. A fabric is disposed over the first resin. A second resin is formed over the first resin and around the fabric to form an asymmetrical pre-impregnated (PPG) substrate. The first carrier is removed. A second carrier is provided and a first conductive layer is formed over the second carrier. A portion of the first conductive layer is removed. The first conductive layer is transferred from the second carrier to the first resin. The first conductive layer is oriented asymmetrically such that the first conductive layer is offset with respect to the fabric to minimize warpage. The second carrier is removed. A via is formed through the second resin and fabric to expose the first conductive layer. A second conductive layer formed in the via over the first conductive layer.Type: ApplicationFiled: December 8, 2011Publication date: June 13, 2013Applicant: STATS CHIPPAC, LTD.Inventors: Hyung Sang Park, Sung Soo Kim, SungWon Cho
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Patent number: RE47170Abstract: Semiconductor patterns are formed by performing trimming simultaneously with the process of depositing the spacer oxide. Alternatively, a first part of the trimming is performed in-situ, immediately before the spacer oxide deposition process in the same chamber in which the spacer oxide deposition is performed whereas a second part of the trimming is performed simultaneously with the process of depositing the spacer oxide. Thus, semiconductor patterns are formed reducing PR footing during PR trimming with direct plasma exposure.Type: GrantFiled: July 12, 2013Date of Patent: December 18, 2018Assignee: ASM IP Holding B.V.Inventors: Julien Beynet, Hyung Sang Park, Naoki Inoue