Patents by Inventor I-Ming Chang
I-Ming Chang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240150192Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Pi CHANG, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Huang-Lin Chao
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Patent number: 11978674Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a first source/drain epitaxial feature formed over a substrate, a second source/drain epitaxial feature formed over the substrate, two or more semiconductor layers disposed between the first source/drain epitaxial feature and the second source/drain epitaxial feature, a gate electrode layer surrounding a portion of one of the two or more semiconductor layers, a first dielectric region disposed in the substrate and in contact with a first side of the first source/drain epitaxial feature, and a second dielectric region disposed in the substrate and in contact with a first side of the second source/drain epitaxial feature, the second dielectric region being separated from the first dielectric region by a substrate.Type: GrantFiled: October 8, 2021Date of Patent: May 7, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Ming Chang, Jung-Hung Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Yao-Sheng Huang, Huang-Lin Chao
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Publication number: 20240084017Abstract: Monoclonal antibodies against human Mac-1 are provided. These antibodies can bind to different states of Mac-1 so as to alter the biofunctions of Mac-1. These antibodies can modulate Th1/Th2 cytokine secretions by TLR-activated immune cells and can be used for the treatments of diseases related to acute and chronic inflammatory disorders, such as infectious diseases, and cancers.Type: ApplicationFiled: December 30, 2021Publication date: March 14, 2024Applicant: Ascendo Biotechnology, Inc.Inventors: Yen-Ta Lu, Chia-Ming Chang, Ping-Yen Huang, I-Fang Tsai, Frank Wen-Chi Lee
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Patent number: 11923032Abstract: The present disclosure provides a circuit for detecting leakage between word lines in a memory device. The circuit includes a first and a second coupling capacitor. A first terminals of the first and second coupling capacitors are connected to a first word line and a second word line, respectively. The first terminals of the first and second coupling capacitors are also connected to a first and a second voltage supply, respectively. The circuit further includes a comparator, wherein a first input of the comparator is connected to a second terminal of the first coupling capacitor and a second input of the comparator is connected to a second terminal of the second coupling capacitor. The comparator is configured to send alarm signal when a differential voltage between the first input and the second input of the comparator is larger than a hysteresis level of the comparator.Type: GrantFiled: November 3, 2021Date of Patent: March 5, 2024Assignee: Yangtze Memory Technologies Co., Ltd.Inventors: Kun Yang, Min She, Albert I. Ming Chang
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Patent number: 11908702Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.Type: GrantFiled: August 19, 2021Date of Patent: February 20, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Pi Chang, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Huang-Lin Chao
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Publication number: 20240047272Abstract: A semiconductor structure includes a first fin structure and a second fin structure, a first dielectric layer disposed over the first fin structure, a second dielectric layer disposed over the second fin structure, a first gate electrode disposed over the first dielectric layer, and a second gate electrode disposed over the second dielectric layer. A thickness of the first dielectric layer and a thickness of the second dielectric layer are equal. The second fin structure includes an outer region and an inner region, and a Ge concentration in the outer portion is less than Ge concentration in the inner portion.Type: ApplicationFiled: October 23, 2023Publication date: February 8, 2024Inventors: I-MING CHANG, CHUNG-LIANG CHENG, HSIANG-PI CHANG, HUNG-CHANG SUN, YAO-SHENG HUANG, YU-WEI LU, FANG-WEI LEE, ZIWEI FANG, HUANG-LIN CHAO
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Patent number: 11894461Abstract: A semiconductor device includes a semiconductor substrate, an interfacial layer formed on the semiconductor substrate, a high-k dielectric layer formed on the interfacial layer, and a conductive gate electrode layer formed on the high-k dielectric layer. At least one of the high-k dielectric layer and the interfacial layer is doped with: a first dopant species, a second dopant species, and a third dopant species. The first dopant species and the second dopant species form a plurality of first dipole elements having a first polarity. The third dopant species forms a plurality of second dipole elements having a second polarity, and the first and second polarities are opposite.Type: GrantFiled: November 29, 2021Date of Patent: February 6, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiang-Pi Chang, Yen-Tien Tung, Dawei Heh, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Tzer-Min Shen, Huang-Lin Chao
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Publication number: 20240030311Abstract: A semiconductor device includes a semiconductor fin, an epitaxial region located on a side of the semiconductor fin, a silicide layer disposed on the epitaxial region, a contact plug disposed on the silicide layer and over the epitaxial region, and a self-align contact (SAC) layer disposed on the semiconductor fin. At least a part of the SAC layer is implanted with at least one implantation element. The semiconductor fin is spaced apart from the contact plug by the SAC layer.Type: ApplicationFiled: July 21, 2022Publication date: January 25, 2024Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: I-Ming CHANG, Yao-Sheng HUANG, Hsiang-Pi CHANG, Lo-Heng CHANG, Yun-Ju FAN, Huang-Lin CHAO
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Patent number: 11842927Abstract: A semiconductor structure includes a substrate including a first region and a second region, a first channel layer disposed in the first region and a second channel layer disposed in the second region, a first dielectric layer disposed on the first channel layer and a second dielectric layer disposed on the second channel layer, and a first gate electrode disposed on the first dielectric layer and a second gate electrode disposed on the second dielectric layer. The first channel layer in the first region includes Ge compound of a first Ge concentration, the second channel layer in the second region includes Ge compound of a second Ge concentration. The first Ge concentration in the first channel layer is greater than the second Ge concentration in the second channel layer.Type: GrantFiled: May 25, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventors: I-Ming Chang, Chung-Liang Cheng, Hsiang-Pi Chang, Hung-Chang Sun, Yao-Sheng Huang, Yu-Wei Lu, Fang-Wei Lee, Ziwei Fang, Huang-Lin Chao
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Publication number: 20230395433Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.Type: ApplicationFiled: June 27, 2023Publication date: December 7, 2023Inventors: Yao-Sheng Huang, I-Ming Chang, Huang-Lin Chao
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Publication number: 20230386938Abstract: A method of forming a semiconductor device includes forming a transistor comprising a gate stack on a semiconductor substrate by, at least, forming a first dielectric layer on the semiconductor substrate, forming a dipole layer on the dielectric layer; forming a second dielectric layer on the dipole layer, forming a conductive work function layer on the second dielectric layer, forming a gate electrode layer on the conductive work function layer. The method also includes varying a distance between dipole inducing elements in the dipole layer and a surface of the semiconductor substrate by tuning a thickness of the first dielectric layer to adjust a threshold voltage of the transistor.Type: ApplicationFiled: August 9, 2023Publication date: November 30, 2023Inventors: Huiching Chang, I-Ming Chang, Huang-Lin Chao
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Publication number: 20230327004Abstract: A semiconductor device includes a semiconductor fin, a gate structure, a doped semiconductor layer, and a dielectric structure. The semiconductor fin has a top portion and a lower portion extending from the top portion to a substrate. The gate structure extends across the semiconductor fin. The doped semiconductor layer interfaces the top portion of the semiconductor fin. In a cross-section taken along a lengthwise direction of the gate structure, the doped semiconductor layer has an outer profile conformal to a profile of the top portion of the semiconductor fin.Type: ApplicationFiled: May 31, 2023Publication date: October 12, 2023Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Sheng HUANG, Hung-Chang SUN, I-Ming CHANG, Zi-Wei FANG
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Patent number: 11735483Abstract: Embodiments of the present disclosure provide a method of forming N-type and P-type source/drain features using one patterned mask and one self-aligned mask to increase windows of error tolerance and provide flexibilities for source/drain features of various shapes and/or volumes. In some embodiments, after forming a first type of source/drain features, a self-aligned mask layer is formed over the first type of source/drain features without using photolithography process, thus, avoid damaging the first type of source/drain features in the patterning process.Type: GrantFiled: February 26, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yao-Sheng Huang, I-Ming Chang, Huang-Lin Chao
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Patent number: 11728414Abstract: A method of forming a semiconductor device comprises forming a fin structure; forming a source/drain structure in the fin structure; and forming a gate electrode over the fin structure. The source/drain structure includes Si1?x?yM1xM2y, where M1 includes Sn, M2 is one or more of P and As, 0.01?x?0.1, and 0.01?y?0.Type: GrantFiled: February 14, 2022Date of Patent: August 15, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yasutoshi Okuno, Cheng-Yi Peng, Ziwei Fang, I-Ming Chang, Akira Mineji, Yu-Ming Lin, Meng-Hsuan Hsiao
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Publication number: 20230246080Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate, the silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer includes an oxide material.Type: ApplicationFiled: April 10, 2023Publication date: August 3, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Wen TSAU, Chun-I WU, Ziwei FANG, Huang-Lin CHAO, I-Ming CHANG, Chung-Liang CHENG, Chih-Cheng LIN
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Patent number: 11710779Abstract: An integrated circuit device is provided that includes a first fin structure and a second fin structure extending from a substrate. The first fin structure is a first composition, and includes rounded corners. The second fin structure is a second composition, different than the first composition. A first interface layer is formed directly on the first fin structure including the rounded corners and a second interface layer directly on the second fin structure. The first interface layer is an oxide of the first composition and the second interface layer is an oxide of the second composition. A gate dielectric layer is formed over the first interface layer and the second interface layer.Type: GrantFiled: April 5, 2021Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chung-Liang Cheng, I-Ming Chang, Hsiang-Pi Chang, Yu-Wei Lu, Ziwei Fang, Huang-Lin Chao
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Patent number: 11705507Abstract: A semiconductor device includes a semiconductor substrate, a semiconductor fin extending from the semiconductor substrate, a gate structure extending across the semiconductor fin, and source/drain semiconductor layers on opposite sides of the gate structure. The source/drain semiconductor layers each have a first thickness over a top side of the semiconductor fin and a second thickness over a lateral side of the semiconductor fin. The first thickness and the second thickness have a difference smaller than about 20 percent of the first thickness.Type: GrantFiled: May 28, 2021Date of Patent: July 18, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Yao-Sheng Huang, Hung-Chang Sun, I-Ming Chang, Zi-Wei Fang
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Publication number: 20230187526Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming an interfacial oxide layer on the fin structure, forming a first dielectric layer over the interfacial oxide layer, forming a dipole layer between the interfacial oxide layer and the first dielectric layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The dipole layer includes ions of first and second metals that are different from each other. The first and second metals have electronegativity values greater than an electronegativity value of a metal or a semiconductor of the first dielectric layer.Type: ApplicationFiled: February 13, 2023Publication date: June 15, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Pi CHANG, Chung-Liang CHENG, I-Ming CHANG, Yao-Sheng HUANG, Huang-Lin CHAO
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Patent number: 11626493Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack includes a gate dielectric layer, a first metal-containing layer, a silicon-containing layer, a second metal-containing layer, and a gate electrode layer sequentially stacked over the substrate. The silicon-containing layer is between the first metal-containing layer and the second metal-containing layer, and the silicon-containing layer is thinner than the second metal-containing layer.Type: GrantFiled: June 11, 2021Date of Patent: April 11, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Wen Tsau, Chun-I Wu, Ziwei Fang, Huang-Lin Chao, I-Ming Chang, Chung-Liang Cheng, Chih-Cheng Lin
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Publication number: 20230058221Abstract: A semiconductor device with different configurations of gate structures and a method of fabricating the same are disclosed. The method includes forming a fin structure on a substrate, forming a gate opening on the fin structure, forming a metallic oxide layer within the gate opening, forming a first dielectric layer on the metallic oxide layer, forming a second dielectric layer on the first dielectric layer, forming a work function metal (WFM) layer on the second dielectric layer, and forming a gate metal fill layer on the WFM layer. The forming the first dielectric layer includes depositing an oxide material with an oxygen areal density less than an oxygen areal density of the metallic oxide layer.Type: ApplicationFiled: August 19, 2021Publication date: February 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiang-Pi CHANG, Chung-Liang Cheng, I-Ming Chang, Yao-Sheng Huang, Huang-Lin Chao